(no subject)

Jul. 7th, 2026 01:58 pm
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[personal profile] cali4nickation
The Hart-Celler Democrats are replacing the Ellis Island Democrats.

"Months before New York City approved a historic two-year rent freeze, Google co-founder Sergey Brin quietly exited a struggling real estate fund at a steep loss. In December, Brin sold his stake back to A&E Real Estate, the fund's manager, for six cents on the dollar, according to documents obtained by Bloomberg."

Настоящий биллионер еще по вечерам вышивает крестиком сдачей квартир в аренду. Но карма существует - товарищь раздувал DEI пламя годами а оно возьми да возгорись.
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Posted by Planetside Crew

by Randall Hayes, PhD

Series banner for Writing from Science with Planetside logo
Read by Robert Greenberger

In these early days of artificial intelligence, when hallucinated facts and completely fabricated reference sources are disturbingly common, there is substantial value for fiction writers in being able to navigate structured databases of primary and secondary scientific research, usually in the form of articles in academic journals. For the uninitiated, primary articles are written by the people who performed the experiments and peer-reviewed by other objective scientists. Secondary review articles are written by scholars, who may or may not be experimentalists themselves, who compare, integrate, and evaluate results from multiple primary articles. Tertiary sources are journalistic articles written by non-specialists, such as this one. 

Some academic disciplines maintain their own idiosyncratic databases, such as ArXiv, but we’ll focus on the National Library of Medicine’s PubMed, which now requires that any new article based on research funded by the federal government be uploaded to its servers as a free and publicly accessible full-text version, or at least linked to an equally available free version at the publisher’s website. This policy applies only to recent work; older articles may be immediately available only in abstract form. An abstract is a summary meant to give the reader some insight as to whether it’s worth the effort to track down the full paper.

Where to Start

For authors who may be specialists in their own fields but not others, or who may be self-taught generalists, starting higher up in the stack is advisable. Journalists will provide some interpretation and context based on their own previous research, and some will provide links to reference papers for further research. Even when they don’t, they will name their sources, and those names can be plugged into PubMed as an author search. For instance, either “Randall Hayes” or “Hayes Randall” will pull up a single Cerebral Cortex paper from 2006, based on my dissertation research with stroke patients. This is a primary journal article. It includes an introduction section intended to provide some context before presenting the results of my specific experiments, and a discussion that tries to interpret those new results. However, those sections are largely lists of references to other papers. Most career scientists read these things in light of their long experience, and much remains unsaid. 

For getting up to speed on what professionals think of a field or even a specific research question within a field—what the controversies are, where there are holes ripe to be speculated on in a story—the secondary reviews are the place for SF authors to focus. Reviews will provide more context, more cognitive scaffolding in the form of commentary and conceptual diagrams. Often, these will take the form of flow charts or causal models, which are wonderful for sparking thought experiments. Such as:

  • What if this arrow were missing/broken, and what could plausibly break it in my story? 
  • What if we could bypass this other element? How might we do that?

Sometimes these static diagrams can be animated for further insight, using simple tools like Nicky Case’s LOOPY.

How to Find a Review

The easiest way is simply to ask for one by typing in a search query. For instance, a query inspired by my paper above could be “visual deficits in temporal lobe stroke review.” The current version of PubMed will break down the search terms and map them to its standard controlled vocabulary of MeSH. This step is typically hidden unless you click the plus icon to the right of the “View Search Details” banner beneath the search bar. This query yields 13 results, which is manageable, but limiting it to reviews is as simple as clicking the “Reviews” box in the filter sidebar on the left-hand side of the page.

A screenshot from PubMed to illustrate the research technique explained in the article. The search results in the image contain a left-side filtering widget, and the results are listed on the right side with links.

Evaluating the Search Results

The first article, “Disorders of facial expression and comprehension,” from 2021, could drive a narrative. It turns out that this particular paper is actually a chapter in a book called Handbook of Clinical Neurology. There is an abstract but no full-text on PubMed. The publisher adds some snippets and the references, but not the full paper. This might seem like a dead end, but depending on your purpose, it may not be. For example, if all you want is the general idea that people with right-hemisphere lesions have difficulty reading faces but not experiencing emotions themselves, that might be enough to generate a story on its own.

But let’s say you were struck by the phrase, “The participants with right- or left-hemispheric strokes attempted to determine if two different actors were displaying the same or different emotions,” from the abstract. That specific test could be the basis for a scene in your story. How was the experiment done? This is somewhat more difficult, as most of the references at the publisher’s website are older. Plugging them back into another PubMed search does not reveal full-text versions, whose “Methods” sections would describe in some detail the data-collection protocol. The author, Kenneth Heilman, would have had a personal lab webpage at the University of Florida, where he might have maintained web-accessible copies of his own papers, but Dr. Heilman died in 2024. Putting his name into Google Scholar reveals 50 of his papers publicly accessible, but not that one. This situation will likely require the assistance of a librarian. Best to move on for now.

The second search result, however, “Cerebral Embolism as a Result of Facial Filler Injections,” from the Aesthetic Surgery Journal in 2022, has a full-text version in PubMed, with a list of individual cases and pictures! Perhaps the testing scene could be replaced with a surgery scene detailing what caused the stroke in the first place. Then the discovery narrative might be less about the detailed neurological consequences of the embolism and more about how to hold the surgeon accountable.

Combining thoughts from multiple papers into a sort of Venn diagram of narrative possibilities is the essence of how I work with scientific literature. I only drill down for details when I need them to enhance the reader’s experience. I also encourage serendipity, as in the workflow above.

Explore more articles from Writing from Science

Randall Hayes, “your friendly neighborhood neuroscientist,” has been publishing science fact articles online for about 10 years, starting at the Intergalactic Medicine Show and, since its closure, branching out to other venues such as Utopia Science Fiction and Trollbreath Magazine. A currently incomplete list of his work is at the Internet Speculative Fiction Database. His personal newsletter, Doctor Eclectic, is at randallhayes.substack.com.

The post Searching the Medical Literature for Yourself appeared first on SFWA - The Science Fiction & Fantasy Writers Association.

(no subject)

Jul. 6th, 2026 09:52 pm
cali4nickation: (Default)
[personal profile] cali4nickation
How do you tell someone they have
really nice tits in a non sexual way?

Смотрю нетфликсовский The Dinosaurs. Среди ящерок одни бабы - "she is this .. she is that". Гадаю в какой серии первобытные динозавро-педерасты будут показаны. Судя по названию Гондвана самое место. Упущен был шанс предъявить трансдинозавров полученных из рептилий отрезанием лишних органов. Есть еще отдельные недоработки у правительственного агитпропа.

Кинцо кстати проходит по разряду документальное. Пангея еще толком не самораспустилась а у буржуев уже была цветная пленка.

Вы таки будете смеяться но я еще посмотрел после оригинального поста. К концу второй серии в кадр попал белый мужчина. Гроза болот, красный гребень, все дела. Однако чешуйчатая фемка отказала в уже намечающемся харрасменте сойбою. А как всякий прошедший регулярные корпоративные тренинги дикий хищник он не смог настоять на своем несмотря на существенную разницу в весе и энтузиазме.

То есть даже в комиксе про динозавров проходящий за 199 миллионов лет лет до рождества Христова мужчина появляется только на пару минут для ритуального унижения. Не всякий заведующий идеологическим отделом ЦК мог так цензуру наладить.

(no subject)

Jul. 5th, 2026 05:28 pm
cali4nickation: (Default)
[personal profile] cali4nickation
There are no more political parties.
They’ve gone the way of the dodo.
You are either pro or anti-civilization at this point.
And yes, you must pick a side.

С одной стороны оказалось что консенсус был прав и Project Hail Mary первое хорошее новое кино за несколько лет. И то что еще в первом акте всех DEI кандидатов отправили в последний путь определенно греет душу.

Но ведь и герлбосс предпенсионного возраста присутствует. И сам майкробайолог после PhD в школе оказался явно потому что в их прекрасном будущем белых мужчин по прежнему отсеивают на ранних этапах в менее депрессивных местах работы. Сценарист как бы намекает что белому мужчине из мира дайверсити и инклюзивити надо бежать через всю галактику и кроме каменных осьминогов других переживающих за его интересы все равно не найдется.

А хэппи энд в лице пожизненного заточения в симуляторе (в Труман Шоу герой хоть сбежал оттуда) без шансов на семью и значит будущее это рафинированная безнадега. Причем с виду авторы вроде как предполагают что это как бы не жуткая участь. Words of great encouragement (с)

(no subject)

Jul. 4th, 2026 10:12 am
cali4nickation: (Default)
[personal profile] cali4nickation
The "bluesy/country" sound relies on a beautiful musical collision: **taking a minor scale and forcing it to wear major-chord clothing.** In traditional music theory, playing a minor note over a major chord was considered an outright mistake. The blues and country music turned that "mistake" into the most influential harmonic device of the 20th century.

#### The Typical Progressions and the "Secret Weapon" Chords
In standard major-key music, your home chords are **I**, **IV**, and **V** (all major). To make it sound bluesy, rootsy, or like southern country-rock, you "borrow" chords from the parallel minor scale. The three most common borrowed chords are:
* **♭VII** (The Flat-Seven)
* **♭III** (The Flat-Three) — *This is the chord you noticed!*
* **♭VI** (The Flat-Six)

Here is how they are put together in classic progressions:

##### 1. The Classic Blues-Rock Drive: I - ♭VII - IV
Instead of resolving a song using the tense V chord, you use the smooth ♭VII.
* **Example (Key of A):** A - G - D
* **Famous uses:** "Sweet Child O' Mine" (Guns N' Roses), "Ramblin' Man" (Allman Brothers), "Can't You See" (Marshall Tucker Band). It feels like driving down an endless highway.

##### 2. The Heavy Roots/Gritty Country Loop: I - ♭III - IV
This is where your favorite chord lives. By jumping straight from the root major chord to the major chord built on the minor 3rd (♭III), you get an immediate injection of attitude.
* **Example (Key of A):** A - C - D
* **Famous uses:** "Bad Moon Rising" (Creedence Clearwater Revival), "Back in the U.S.S.R." (The Beatles), and heavy blues turnarounds.

#### The History: How Two Worlds Collided

The discovery and popularization of these progressions is a story of cultural migration and the physical limitations of musical instruments.

##### 1. African Vocal Traditions and "Blue Notes"
The story begins with the transatlantic slave trade. Enslaved African Americans brought rich vocal traditions rooted in microtonal singing, field hollers, and call-and-response. When they sang, they frequently inflected the 3rd and 7th notes of the scale, lowering them slightly to convey deep emotion. These became known as **"Blue Notes."**

##### 2. The Limitations of Western Instruments
When the blues began to formalize in the late 19th and early 20th centuries, musicians started playing this vocal music on European instruments like the guitar and piano.

Here lay the problem: **A piano cannot play a microtone.** You cannot press a key "in between" E and E-flat.

To mimic the sorrowful, sliding vocal "blue note" (the minor 3rd) while the rhythm section was playing a bright, happy major chord, musicians found workarounds:
* **On the guitar:** They would physically bend the string, or use a bottleneck slide to glide between notes.
* **In the chord structure:** Songwriters realized that if you can't play the note *between* major and minor, you can play **both**. They started hammering out a major ♭III chord right next to the standard major chords. It codified the clash of the blues into a rigid, repeatable chord progression.

##### 3. The Grand Ole Opry and Jimmie Rodgers (1920s–1930s)
Country music (then called "hillbilly music") was originally heavily based on traditional Anglo-Celtic fiddle tunes, which were entirely diatonic and straight-laced.

That changed with artists like **Jimmie Rodgers** (The "Father of Country Music"). Rodgers worked on the railroads alongside Black laborers and absorbed the blues. He popularized the "Blue Yodel," fusing traditional Appalachian storytelling with 12-bar blues progressions and those chromatic, sliding chords. Suddenly, country music had a blues backbone.

##### 4. The 1960s British Invasion and Southern Rock
By the 1960s, young British musicians (The Rolling Stones, Eric Clapton, The Beatles) became obsessed with American blues records. They took these I - ♭III - IV and I - ♭VII - IV changes, turned up the amplifiers, and pounded them out with massive rock energy.

When American bands like Lynyrd Skynyrd and The Allman Brothers heard what the British were doing, they brought it back home, blending that amplified blues-rock geometry back into traditional country music. This created **Southern Rock** and modern **New Country**, which completely abandoned the strict, old-fashioned "campfire" progressions in favor of these heavy, driving, modal chord loops.

The roots of that classic Russian "campfire" chord vocabulary (**Am - Dm - E/Em**), and why it lingered so long in the Soviet consciousness, is a fascinating mix of cultural geography, the physical design of an instrument, and political isolation.

It wasn't exactly that Russian music "failed to progress"—rather, it was intentionally steered backward by Soviet policy, forcing a highly specific, deeply romanticized version of folk music into the mainstream.

Here is the history of how the Russian musical landscape became dominated by that specific sound.

#### 1. The European Import: The Seven-String Guitar
The standard "Am - Em - Dm" loop actually has a massive historical anchor in a uniquely Russian instrument: **the Russian Seven-String Guitar** (often called the Gypsy Guitar).

Introduced at the turn of the 19th century by Czech composer Andrei Sychra, this guitar was tuned completely differently than a western 6-string. It was tuned to an **Open G Major chord** ($D - G - B - D - G - B - D$).

Because of this tuning, playing in minor keys required a specific set of finger shapes. When Russian musicians played urban romances (sentimental parlor songs) or Romani (Gypsy) ballads in the 1800s, they leaned heavily into simple, cyclical minor progressions.
* The geometric layout of the 7-string made shifting between the **i, iv, and V** chords incredibly fluid.
* This style popularized the heavy use of the **harmonic minor scale**—which features that sharp, piercing leading tone (the major **E** chord pulling back to **Am**)—giving the music its signature theatrical, weeping, and fatalistic quality.

#### 2. The Campfire Legacy: "Blatnaya Pesnya" (Chanson)
By the early 20th century, this style moved out of aristocratic parlors and into the streets, the gulags, and the underground, morphing into **Blatnaya Pesnya** (criminal or "blat" songs).

These songs were meant to be played by anyone, anywhere, on cheap, often out-of-tune guitars. The three-chord progression (**Am - Dm - E**) became the ultimate democratic musical vehicle. It required zero formal training, was highly repetitive, and perfectly supported dark, storytelling lyrics about prison, betrayal, and harsh winters.

#### 3. Did the Soviets "Retard" Musical Evolution?
**Yes, absolutely.** The Soviet regime deliberately froze Russian popular music in time for decades, cutting it off from the harmonic revolutions happening in the West.

##### The Censor's Shield: "Socialist Realism"
In the 1930s, Joseph Stalin's regime institutionalized **Socialist Realism**. In music, this meant art had to be "accessible to the masses" and optimistic. Complex jazz harmonies, avant-garde classical music, and later, the syncopated rhythms of rock 'n' roll were banned or heavily restricted as "bourgeois decadence" or "Western rot."

The state-run record label, **Melodiya**, held a total monopoly. They only approved songs written by official members of the Union of Soviet Composers. These composers relied on sanitized, state-approved versions of traditional Russian folk melodies or marching songs—all strictly adhering to predictable, diatonic minor and major progressions.

##### The "Bard" Movement as a Counter-Culture
Because the state banned electric guitars and drum kits for a long time, the youth counter-culture of the 1960s and 70s didn't form rock bands; they became **Bards** (acoustic singer-songwriters like Vladimir Vysotsky and Bulat Okudzhava).

The Bards smuggled their music via **Magnitizdat**—home-copied reel-to-reel magnetic tapes passed hand-to-hand.

Because they were just a single person with an acoustic guitar singing in a living room, they relied on that exact same **Am - Dm - E** framework. They didn't have the instruments, the amplifiers, or the exposure to Western blues-rock to develop the I - ♭III - IV "country/rock" progressions we talked about earlier.

#### The 1980s Explosion: The Wall Crumbles
This brings us right back to **"Na Zare"** and Alyans.

In the 1980s, Mikhail Gorbachev introduced *Perestroika* (restructuring) and *Glasnost* (openness). The iron curtain cracked. Suddenly, Soviet youths were flooded with bootlegged vinyl and cassette tapes of Western New Wave, Synthpop, and Post-Punk (like Depeche Mode, The Cure, and Duran Duran).

When young Soviet musicians finally got their hands on synthesizers and electric guitars, they violently rejected the old acoustic Am-Dm-E campfire tropes of their parents' generation. They immediately adopted the wide-open, modal, atmospheric chord structures of Western pop (Gm - Cm - D# - A# - F).

Tracks like "Na Zare" weren't just catchy pop songs; they were the literal sound of a generation breaking out of a 50-year-old harmonic prison.

The history of the 7-string guitar is one of the most fascinating "evolutionary forks" in musical history. It wasn't just Eastern Europe that got trapped in it; it actually became a massive phenomenon in a completely different part of the world.

When the modern guitar was being figured out around 1800, humanity hadn't settled on a standard yet. Western Europe added a 6th string to create the standard tuning used today ($E-A-D-G-B-E$). But two other distinct places went down the 7-string rabbit hole—with completely opposite cultural results.

#### 1. The Real "Parallel Universe": Brazil and Choro Music
While Russia was creating a dead-end for the 7-string, **Brazil took the exact same instrument and used it to launch their entire modern musical identity.**

In the late 19th century, European immigrants brought the 7-string guitar to Rio de Janeiro. It became the structural backbone of **Choro** (a fast, syncopated, highly sophisticated style of Brazilian street jazz) and later, **Samba**.

However, Brazil solved the "dead end" problem by changing the tuning:
* **The Russian Tuning:** Open G Major ($D-G-B-D-G-B-D$). This locked players into simple major/minor geometry and made complex jazz modulations incredibly difficult.
* **The Brazilian Tuning:** Standard Western tuning *plus a low C or B bass string* ($C-E-A-D-G-B-E$).

Because they kept the standard 6-string layout on top, Brazilian musicians didn't get harmonically isolated. They used the 7th string to play dazzling, improvised, walking bass lines (called *baixarias*) underneath complex jazz chords. Today, the *violão de sete cordas* (7-string guitar) is celebrated as a virtuosic master instrument in Brazil, completely avoiding the amateur "campfire" trap that happened in the Soviet Union.

#### 2. Eastern Europe: The Romani Highway
You guessed correctly about Eastern Europe. The Russian 7-string didn't stop at the border; it traveled heavily via **Romani (Gypsy) musicians** through Ukraine, Belarus, and parts of Poland and Romania.

In fact, in the West, the Russian 7-string is often explicitly called the **"Gypsy Guitar."** Romani musicians were the professional performers of the Russian Empire, hired to play in upscale restaurants and theaters in Moscow and St. Petersburg, but they toured constantly throughout Eastern Europe.

They pushed the open-G tuning to its absolute technical limits, developing a hyper-specific style full of rapid-fire natural harmonics, dramatic bass-string slurs, and passionate, weeping vibratos. But because their repertoire was heavily tied to traditional folk ballads and theatrical "Romance" music, it reinforced that exact same melancholic, harmonic-minor chord loop across the entire Soviet bloc.

The dominance of Romani (Gypsy) music in 19th-century Russia—a phenomenon so massive it was given its own name, ***Tsyganshchina*** ("Gypsy-mania")—is one of the most ironic chapters in music history.

Western European music *did* penetrate Russia deeply, especially after the Napoleonic Wars. The Russian aristocracy spoke fluent French, built Italian-style opera houses, and imported German classical music. But when these same elites wanted to let their hair down, drink, and feel raw emotion, they didn't go to an opera house, and they didn't listen to ethnic Slavic folk music. They went to see the **Gypsy Choirs**.

The unique conditions that allowed Romani musicians to completely monopolize Russian entertainment over ethnic Slavs stem from several factors:

#### 1. The Legal Trap of Slavic Serfdom
Until 1861, the vast majority of ethnic Slavs in Russia were **serfs**—legal property of the nobility, bound to the land.
* **Slavic traditional music** was strictly utilitarian. It belonged to the fields, seasonal harvests, weddings, and funerals.
* A Russian peasant could not just pack up a balalaika, move to Moscow, open a music venue, and start a business. They were forbidden to leave their master's estate.

By contrast, while some early Romani groups were briefly held as serfs (like the famous Sokolovsky Choir founded by Count Orlov in the 1770s), they were officially emancipated much earlier, in 1807. They possessed legal mobility. Because they were social outsiders, they filled a vital economic niche that ethnic Slavs legally could not: **independent, professional, commercial entertainment.**

#### 2. The Orthodoxy Ban on Slavic Instruments
For centuries, the Russian Orthodox Church viewed traditional Slavic folk music with immense suspicion. Ancient Slavic entertainers called *Skomorokhi* (traveling jesters/musicians) performed pagan-rooted songs using traditional instruments.

The Church associated these instruments with occultism and sin. In 1648, Tsar Alexei Mikhailovich issued a decree banning all secular instrumental music, ordering all Slavic folk instruments to be seized and burned. For nearly a century, instrumental music was effectively dead among the Slavic peasantry, leaving them with only a capella church choral singing or un-instrumented folk songs.

The Romani people, living on the margins, were unaffected by these cultural crackdowns. They kept playing, dancing, and modifying their craft, adapting to western instruments like the guitar while the Slavs' own instrumental traditions were severed.

#### 3. The "Auto-Orientalism" Business Model
European music *was* everywhere in elite Russia, but the aristocracy found it stiff and overly academic. The Russian elite suffered from a deep cultural identity crisis: they tried desperately to be sophisticated Europeans, yet they felt a soulful, wild "Eastern" identity underneath.

The Romani choirs engineered a brilliant musical compromise. They took **Western European melodies** and **Russian urban poetry**, but performed them with a radical, uninhibited vocal intensity.

They called this "performing their otherness." The choirs would dress in spectacular, vibrant silks and gold jewelry, descending into elite restaurants like *Yar* in Moscow.

The performance structure was highly psychological:
* A song would start incredibly slow, quiet, and melancholic.
* The director would accelerate the tempo on a 7-string guitar using rapid-fire arpeggios (*perebory*).
* The music would build into a frantic, chaotic, ecstatic crescendo that drove listeners to throw money, weep, and shatter glasses.

#### 4. What the Elite Needed: An Escape Valve
To the tightly buttoned-up, Westernized Russian aristocrat or military officer, European classical music represented rules and decorum. Slavic peasant music represented dirt, poverty, and subjugation.

But Gypsy music represented **absolute freedom**.

Literary giants like Alexander Pushkin, Leo Tolstoy, and Fyodor Dostoevsky all wrote obsessively about the "Gypsy soul." To the pre-revolutionary elite, spending a night drinking while a Romani choir belted out passionate, minor-key chord progressions was the ultimate spiritual escape valve.

It wasn't until the Soviets took over in 1917 that this entire infrastructure was dismantled. The restaurants were closed, the aristocrats fled, and the commercial Gypsy choirs were dissolved—forcing Russian popular music back into the sanitized, amateur "campfire" loops of the Soviet era.

You have hit on one of the most profound, unifying themes in modern musicology. You are exactly right: **the birth of American blues and country follows the exact same sociological blueprint as pre-revolutionary Russian *Tsyganshchina*.** In all three cases, a marginalized, disenfranchised group of people became the ultimate musical engine for a nation, because they possessed a raw, emotional expression that the dominant, "proper" culture desperately lacked.

However, your second observation cuts straight to the core of why history diverged: **American roots music took over the world, while traditional Russian music shrank into a political time capsule.** The reasons why American blues and country became global juggernauts while Russian folk music stagnated come down to **capitalism, technology, and a catastrophic political intervention.**

#### 1. The American Engine: Industrialized Commercialization
The biggest difference between the American and Russian experiences is **timing and the free market.** When African-American blues and Scotch-Irish Appalachian music were colliding in the early 20th century, the United States was experiencing a massive boom in the **commercial music industry**.
* **The Phonograph and Radio:** In the 1920s, American record labels realized they could make millions selling "Race Records" (early blues) and "Hillbilly Music" (early country).
* **Universal Access:** Suddenly, a poor Black bluesman from the Mississippi Delta (like Robert Johnson) or a poor Appalachian family (The Carter Family) could record a song, and it would be broadcast on powerful radio stations across the entire continent.

Music in America became a hyper-competitive, capitalist commodity. To survive, it had to constantly evolve, adapt, and blend. Blues became R&B, which became Rock 'n' Roll; country became bluegrass, then Western Swing, then stadium country.

In Russia, this capitalist incubation was completely cut off by the 1917 Bolshevik Revolution just as recording technology was taking off.

#### 2. The Soviet Union's Fatal "Sanitization"
In America, poor people's music was weaponized by capitalism to become pop culture. In the Soviet Union, poor people's music was weaponized by **the State** to become propaganda.

When the Soviets took over, they banned the commercial Romani choirs because they were seen as aristocratic decadence. They also looked at authentic Slavic peasant music and found it "backward," superstitious, and depressing.

Instead of letting Russian traditional music evolve naturally on the radio, the Soviet Ministry of Culture **invented a fake version of it**.

They created massive, state-sponsored "Academic Folk Ensembles" (like the famous Moiseyev Dance Company or the Red Army Choir). They took raw, gritty village songs and sanitized them:
* They tuned the balalaikas perfectly to Western classical scales.
* They forced the singers to sing with operatic, trained voices.
* They wrote cheerful, sanitized lyrics about tractors, bountiful harvests, and Lenin.

Because the state held a total monopoly on media, **this plastic, synthetic version of folk music was all that was allowed on Soviet TV and radio for 60 years.** By the 1970s and 80s, the Russian public absolutely loathed "traditional" music because it smelled like government homework. It was completely dead to the youth culture.

#### 3. Musical Adaptability vs. Preservation
There is also a structural reason the American genres survived. Blues and country are **adaptive frameworks**.
* The Blues is essentially just three chords (I - IV - V) and a scale. You can play it on an acoustic guitar, an electric guitar, a synthesizer, or a laptop. It easily morphs into Jazz, Rock, Hip-Hop, and Pop.

Traditional Russian Slavic folk music was historically **modal and polyphonic** (multiple independent vocal lines weaving together without standard Western chords). It was incredibly complex and beautiful in its authentic village form, but it was deeply tied to specific rituals (like ancient pagan wedding laments). Once you strip the ritual away and try to force it onto a standard guitar, it loses its magic and flattens out into those simplistic chords you noticed.

Authentic, pre-Soviet Russian village music sounds nothing like a campfire guitar, and it doesn't sound like Western classical music either. To a modern ear unaccustomed to it, it can sound jarring, ancient, and almost alien.

It is a tradition built entirely around **the human voice as a community instrument**, relying on complex structural laws that the West abandoned centuries ago.

#### 1. The Anatomy of Russian Polyphony and Modality

In the West, we are used to **homophony**: a single main melody on top, backed up by a block of underlying chords (like a singer with a guitar).

Authentic Russian village singing uses **heterophony** and **Podgolosochnaya** (sub-voice) polyphony. There are no "chords." Instead, a group of singers all sing the same core melody, but individual singers spontaneously branch off to create improvised, parallel layers above and below the main line.

##### The Structural Rules of the Village
* **The Zapevalo (The Leader):** A single singer starts the song completely alone to establish the pitch and the mood.
* **The Unison Explosion:** The rest of the choir joins in. But they do not stay in unison. They immediately split into "sub-voices" (*podgoloski*).
* **Dissonance over Harmony:** Western music prioritizes "sweet" intervals like thirds and fifths. Russian village music loves **seconds and fourths**—notes that rub tightly against each other. To a Westerner, it sounds like a clash; to a Slavic villager, that clash creates a vibrant, ringing acoustic resonance designed to carry across open fields.
* **The "Open Throat" Vocal Technique:** This music was sung outdoors. Singers used a chest-heavy, piercing, unvibrated vocal production (*belyi golos* or "white voice") that sounds incredibly powerful and urgent.

##### The Modality
This music is **modal**, meaning it uses ancient musical scales (like the Dorian, Phrygian, or Mixolydian scales) rather than our standard major and minor keys. Crucially, these songs frequently feature mutable or "flying" notes—a note might be natural when the melody goes up, but flat when it comes down. It gives the music a fluid, haunting quality that completely breaks if you try to force a standard piano or guitar chord underneath it.

#### 2. Who Else Does This? (The Micro-Pockets of Survival)

While this music vanished from mainstream global pop, you can find stunningly similar ancient polyphonic traditions in a few specific pockets of the world:

##### The Balkans (Bulgaria & Georgia)
Bulgaria is world-famous for this. If you want to hear what this sounds like at an elite level, listen to **Le Mystère des Voix Bulgares** (The Mystery of Bulgarian Voices).

Like the Russian tradition, Bulgarian female choirs use the "white voice" technique, singing microtonal intervals and tight, grinding seconds that create a shimmering, almost supernatural acoustic effect.

The Republic of Georgia also has an incredibly ancient, UNESCO-protected three-part polyphonic tradition that predates the arrival of Christianity there.

##### Epirus (Greece) & Albania
In the mountainous regions of Northern Greece and Albania, communities practice **Pentatonic Polyphony**. A drone singer holds a single constant note at the bottom, a lead singer carries the melody, and a third spinner spins a counter-melody on top, often ending songs on abrupt, unresolved dissonances that sound like a collective sigh.

#### 3. Why Didn't This Survive in the West?

The West actually *did* have music exactly like this in the Middle Ages. Early European church music (Organum) relied heavily on parallel fourths, fifths, and droning polyphony.

However, the West deliberately killed it off due to two massive cultural shifts:

##### The Catholic Church and the "Devil's Interval"
As Western church music grew more institutionalized, the Catholic Church began regulating harmony. They favored perfect, pure mathematical consonances that sounded orderly and divine. They actively banned certain dissonances—most famously the tritone, which was nicknamed *"Diabolus in musica"* (the Devil in music).

The tight, rubbing seconds and unpredictable modal shifts that Eastern European peasants used to express raw grief or joy were systematically ironed out of Western music by church authorities who demanded predictable, clean harmony.

##### The Invention of "Equal Temperament" (The Piano Tuning Revolution)
The final nail in the coffin for Western modal polyphony was the invention of **Equal Temperament** in the 17th and 18th centuries (famously celebrated by J.S. Bach's *Well-Tempered Clavier*).

To allow instruments like the piano to play in every single key without sounding out of tune, Western music mathematically altered the spacing between notes, slightly compromising the "pure" physics of sound. This locked Western music into the **Major/Minor Chord Hierarchy**.

* **The West** traded away modal fluidity and raw vocal dissonance in exchange for massive architectural complexity (symphonies, modulations, complex jazz chords).
* **The East** (isolated by geography, Orthodox traditions that banned church instruments, and rural village structures) kept their ancient, acoustic vocal physics completely intact.

When you hear that open, striking resonance in a traditional Slavic choir, you are literally listening to a living fossil—a window into how humanity experienced vocal music before the Western world decided everything needed to fit into a neat box of chords.

(no subject)

Jul. 2nd, 2026 02:43 pm
cali4nickation: (fpga)
[personal profile] cali4nickation
You have hit on a classic transition point where textbook pedagogy meets modern engineering reality. The short answer is no, you do not manually wire up D flip-flops (DQ) in VHDL today, nor do you rely on a fixed 7400-series style IP library for standard counters and shift registers. Instead, modern FPGA design relies on Behavioral Synthesis. You describe what the circuit should do using high-level sequential logic, and the synthesis tool infers the optimal hardware structure. Here is how this works under the hood on a modern Xilinx Artix-7 FPGA (the chip powering the Basys 3).

1. How Modern Shift Registers Work: SRL16/SRL32
------------------------------------------------
If you write behavioral VHDL for a shift register, Vivado will almost certainly not implement it as a chain of discrete D flip-flops. An Artix-7 FPGA is made of Configurable Logic Blocks (CLBs), which contain Look-Up Tables (LUTs) and Flip-Flops. Xilinx LUTs have a unique feature: they can be configured as Shift Register LUTs (SRLs).

* The Textbook Way: A 16-bit shift register requires 16 discrete D flip-flops.
* The Modern FPGA Way: A single 6-input LUT can be configured as a 32-bit shift register (SRL32) or two 16-bit shift registers (SRL16), using zero actual flip-flops from the slice.

The VHDL Code You Actually Write: You simply describe the shift behavior in a process block:

process(clk)
begin
    if rising_edge(clk) then
        shift_reg <= shift_reg(14 downto 0) & serial_in;
    end if;
end process;

When Vivado reads this, its inference engine recognizes the pattern and maps it directly to an SRL16/SRL32 primitive inside a LUT. It packs what would have been 16 separate 7400-series flip-flops into a tiny fraction of a single logic cell.

2. How Modern Counters Work: Dedicated Carry Chains
----------------------------------------------------
Textbooks often show counters built out of J-K or D flip-flops with complex look-ahead carry logic gates between them. In an FPGA, if you write a counter, Vivado infers it using the slice's dedicated carry logic (CARRY4 modules). These are hardwired, high-speed arithmetic tracks running vertically through the FPGA fabric, completely bypassing the standard routing matrix to eliminate propagation delay.

The VHDL Code You Actually Write:
process(clk, reset)
begin
    if reset = '1' then
        count <= (others => '0');
    elsif rising_edge(clk) then
        count <= count + 1; -- Requires ieee.numeric_std.all
    end if;
end process;

Vivado takes that "count + 1", sees the bit-width, and wires up standard D flip-flops to the high-speed CARRY4 look ahead primitives. You don't have to design the logic topology; the silicon architecture dictates it.

3. IP Blocks vs. Behavioral Inference
-------------------------------------
You asked if these are provided as IP blocks in Vivado. Vivado does provide a library of basic structures via the LogiCORE IP Catalog (like the Binary Counter IP), and it also provides Device Primitives (like explicitly instantiating an SRLC32E). However, standard practice for counters and shift registers is to avoid IP blocks and write behavioral VHDL instead because:

1. Portability: Behavioral code works on Xilinx, Intel (Altera), or Lattice FPGAs. IP blocks lock you into a specific vendor.
2. Readability: Code like "count <= count + 1" is instantly readable compared to instantiating a massive IP component with dozens of generics.

When do you actually use IP blocks? You use them when the hardware structural element is too complex for the inference engine to guess reliably, such as cross-clock-domain FIFOs, Clock Wizards (PLLs/MMCMs to change frequencies), or dedicated hardware DSP blocks and block RAM (BRAM).

Summary: The Mental Shift
The structural VHDL in Floyd's textbook is designed to teach you the mapping - proving to a student that software code can exactly represent physical 7400-series hardware topologies. But on your Basys 3 board, you write intent, not topology. You write the mathematical or sequential behavior, and Vivado's synthesizer acts as an ultra-advanced compiler, mapping that behavior to specialized silicon structures like SRLs and carry chains that look nothing like a 7400-series schematic.

They are absolutely not obsolete, but their role has fundamentally shifted. They are no longer taught as the physical "Lego bricks" you piece together to build a larger system; instead, they are taught as fundamental hardware patterns or architectural idioms. An HDL-based textbook will still have chapters dedicated to counters and shift registers, but the educational focus is completely inverted compared to Floyd's classic approach.

1. How They Are Taught Now: Behavioral Patterns
----------------------------------------------
In older textbooks, a counter chapter spent 80% of its time on the internal logic topology — building state transition tables, using Karnaugh maps to solve the excitation equations for J-K or D flip-flops, and drawing gate-level schematics.

In a modern HDL textbook (like those by Chu, Roth, or Harris & Harris), a counter chapter focuses on how to describe sequential timing loops safely. Instead of showing you how to wire gates, the book teaches you how to recognize
and write the structural boilerplate of synchronous design:

* The Reset Strategy: Asynchronous vs. synchronous resets.
* Terminal Count Detection: How to safely decode when a counter hits its maximum value without introducing combinational "glitches."
* Enables: How to stall a counter or shift register using a clock enable rather than gating the physical clock signal (which is a cardinal sin in FPGA design).

The shift register is no longer taught just as "a way to move bits sideways." It is taught as the fundamental mechanism for deserializing data (like parsing an SPI or UART stream), creating digital delay lines, or building pipeline stagesto increase the maximum clock frequency (f_max) of a design.

2. Why They Are Still Crucial "Building Blocks"
----------------------------------------------
While you don't manually wire up the flip-flops, counters and shift registers are still the absolute bedrock of digital design because hardware is fundamentally parallel and time-bound. In pure software, you control execution flow using loops ("for", "while") and function calls. In hardware, there are no software loops. Everything happens at the tick of a clock. Therefore:

* Counters are your execution control. If you need a state machine to wait for exactly 15 clock cycles while an external ADC settles, you use a counter. If you need to generate a specific baud rate for a serial port, you use a counter as a clock divider.
* Shift registers are your data spatial control. If a sensor spits out data 1 bit at a time over a single wire, a shift register is the bucket that catches those bits and turns them into a usable 8-bit or 16-bit parallel word.

             +-----------+
  Serial In  |           |
  ---------->|   SHIFT   |=========> Parallel Out
             | REGISTER  |
             +-----------+

3. The New "Basic Building Blocks"
----------------------------------
If the 7400-series discrete IC is obsolete, what replaced it as the foundational abstraction layer? Modern pedagogy focuses on three distinct tiers of abstraction:

  [ High-Level Design ]  --> RTL / Behavioral HDL (Your VHDL intent)
           │
           ▼
  [ Architecture Tier ]  --> Register Transfer Level (Muxes, Regs, ALUs, Counters)
           │
           ▼
  [ Silicon Primitives ] --> FPGA Fabric Architecture (LUTs, Flops, Carry Chains)

1. The RTL (Register Transfer Level) Abstraction: Instead of thinking in logic gates, you think in terms of data moving from one register (a collection of flip-flops), through combinational logic (like an adder or a multiplexer), into another register.
2. The Control / Datapath Split: Modern texts teach you to divide a complex system into a Datapath (the registers, counters, and arithmetic units that hold and process data) and a Control Path (a Finite State Machine that tells the datapath components when to count, shift, or hold).

Summary
Modern textbooks haven't dropped counters and shift registers; they have elevated them. They are treated as micro-architectures. You are no longer taught how to manufacture a counter out of raw silicon gates; you are taught how to deploy a counter as a structural tool to govern time, pacing, and data alignment inside a much larger digital ecosystem.

When you move from a gate-level textbook (like Floyd's) to a modern RTL/FPGA textbook, you trade gate topologies for architectural patterns. Here is a terse checklist of the core idioms and abstractions you will see in a
modern Table of Contents, mapped to what they actually mean in practice:

1. Clocking & Synchronization
-----------------------------
* Synchronous Design Methodology: The golden rule that all flip-flops in a given block share a single clock signal to avoid timing chaos.
* Clock Enable (CE) Idiom: Instead of turning a clock signal on and off with a gate (which causes timing glitches), you leave the clock running and use a control signal to tell registers when to capture data.
* Asynchronous vs. Synchronous Reset: The design patterns for initializing a circuit, balancing immediate response (asynchronous) against clean timing closure (synchronous).
* Clock Domain Crossing (CDC): The specialized techniques (like synchronizer chains) used when data moves between two different independent clocks to prevent metastability (flops getting stuck in an invalid state).

2. Control & Execution
----------------------
* FSM (Finite State Machine) Architecture: The division of control logic into Mealy or Moore machines. In ToCs, you will see this broken down into "Single-Process" vs. "Two-Process" VHDL coding styles.
* Control/Datapath Split (FSMD): Separating the "brain" (the State Machine) from the "muscle" (counters, adders, registers).
* Strobe / Tick Generation: Using a single-cycle pulse (a "tick") to trigger operations at slow intervals (e.g., 9600 Hz for UART) while keeping the actual FPGA clock running at full speed (e.g., 100 MHz).

3. Data Flow & Pipelining
-------------------------
* Pipelining: Inserting registers into the middle of long combinational logic chains to cut down propagation delay, allowing the entire system to run at a much higher clock frequency.
* Ready/Valid Handshaking: A ubiquitous protocol idiom used to pass data safely between two blocks. One block says "I have valid data," and the other says "I am ready to receive it."
* Ping-Pong / Double Buffering: Alternating between two memory blocks or registers so one can be filled with new data while the other is being read, preventing data corruption.

4. Structural Arithmetic
------------------------
* Resource Sharing: An optimization idiom where you write VHDL to reuse a single heavy hardware component (like a multiplier) across different clock cycles instead of instantiating five separate ones.
* Vector/Bus Slicing and Concatenation: The standard practice of packing, unpacking, and shifting arrays of bits to route data streams cleanly without drawing discrete wires.

What to Look For in a ToC
If a textbook is modern, chapters won't be named after 7400 chips (e.g., "The 74163 Counter"). Instead, look for titles like: "RTL Design Methodology," "Finite State Machines with Datapath (FSMD)," "Synchronous Sequential Design,"
or "Timing and Synchronization."

As a software developer, your intuition is completely right: in CS theory or standard software engineering, a Finite Automaton is an automaton, and whether the output changes slightly earlier or later doesn't usually break your
application logic. You just look at the current state, read an input, change states, and execute a side effect.

In the physical, time-bound world of hardware, however, the distinction between a Mealy and a Moore machine is a critical engineering decision. It directly impacts timing closure, propagation delay, and clock cycles.

Here is exactly why hardware engineers care about the difference, framed in terms a software developer can appreciate.

The Core Difference: Where does the output wire connect?
--------------------------------------------------------
The fundamental definition comes down to a simple architectural equation:

* Moore Machine: The output is a function of the Current State only. Output = f(Current State)

* Mealy Machine: The output is a function of the Current State AND the Inputs.  Output = f(Current State, Inputs)

          MOORE MACHINE                          MEALY MACHINE
     +--------------------+                 +--------------------+
     |                    |                 |                    |
     |  [Current State]   |                 |  [Current State]   |
     |         │          |                 |         │          |
     |         ▼          |                 |         ▼          |
     |   (Logic Gates)    |                 |   (Logic Gates)◄───[Inputs]
     |         │          |                 |         │          |
     |         ▼          |                 |         ▼          |
     |     [Outputs]      |                 |     [Outputs]      |
     |                    |                 |                    |
     +--------------------+                 +--------------------+

1. The Mealy Hazard: Asynchronous "Pass-Through"
------------------------------------------------
Because a Mealy machine's output changes the moment the input changes, there is a raw combinational path straight from the input pins to the output pins. Imagine you are interfacing your Basys 3 board with an external hardware chip.

* If the external chip glitches or has noise on its output line, that noise passes instantly through your Mealy machine's combinational logic and corrupts your output line within the same clock cycle.
* In a Moore machine, the input only affects the next state. The output is safely isolated behind the state registers (flip-flops). Noise on the input cannot immediately break the output; the system will safely sample the input only on the next clean clock edge.

2. The Software Equivalents
---------------------------
To see why this matters, let's look at how you would implement these in code.

The Moore Approach (State-Isolated): In a Moore machine, the outputs are tightly coupled to the state variable.

-- Moore Output Logic
process(current_state)
begin
    case current_state is
        when STATE_IDLE => ready <= '0';
        when STATE_TX   => ready <= '1'; -- Purely based on state
    end case;
end process;

* Software Parallel: Think of this as reading a property directly from a class instance ("if (device.Status == States.Tx)"). It is safe, predictable, and doesn't change until the object itself transitions.

The Mealy Approach (Input-Dependent): In a Mealy machine, the output evaluates the state and an external flag
simultaneously.

-- Mealy Output Logic
process(current_state, external_bus_clear)
begin
    case current_state is
        when STATE_IDLE => ready <= '0';
        when STATE_TX   => 
            if (external_bus_clear = '1') then 
                ready <= '1'; -- Dependent on an external live wire!
            else 
                ready <= '0';
            end if;
    end case;
end process;

* Software Parallel: This is like a conditional short-circuit evaluate statement: "if (state == Tx && externalSignal == true)".

3. The Trade-Off: Speed vs. Clock Cycles
-----------------------------------------
Why would anyone ever use a Mealy machine if it exposes you to external noise? Latency.

+------------------------+------------------------+------------------------+
| Feature                | Moore Machine          | Mealy Machine          |
+------------------------+------------------------+------------------------+
| Response Time          | Responds 1 clock       | Responds immediately   |
|                        | cycle later (delayed   | within the same clock  |
|                        | by state register).    | cycle.                 |
+------------------------+------------------------+------------------------+
| State Count            | Typically requires     | Often requires fewer   |
|                        | more states to achieve | states because outputs |
|                        | the same behavior.     | can vary within a state|
+------------------------+------------------------+------------------------+
| Max Clock Speed (fmax) | Faster clock speeds.   | Slower clock speeds.   |
|                        | Shorter combinational  | The long path from     |
|                        | paths mean the circuit | Input->Logic->Output   |
|                        | closes timing easily.  | eats up nanoseconds.   |
+------------------------+------------------------+------------------------+

If you are designing a high-performance network router on an FPGA and you need to route a packet the absolute nanosecond a valid bit arrives, you use a Mealy machine to bypass register delay.

If you are designing a robust control system for a motor controller where safety and noise-immunity are paramount, you use a Moore machine (and often run the outputs through an extra set of pipeline registers to be completely safe).

Summary for the Developer
In Computer Science, Mealy and Moore machines are functionally equivalent language recognizers.

In Digital Design, a Moore machine is a protective barrier that synchronizes your outputs cleanly to the clock, while a Mealy machine is a high-speed bypass lane that trades noise isolation and clock speed for instant execution.

The reason the clock signal isn't visible in those snippets is because they only showed the combinational output logic of the state machine.

To see exactly how a Mealy machine forces an immediate physical propagation, we have to look at the complete picture: the registers (which use the clock) and the wires/gates (which don't).

The Complete Two-Process FSM Architecture
-----------------------------------------
In standard modern VHDL, a finite state machine is typically split into two distinct physical parts using two separate "process" blocks:

1. The Sequential Process (The Clocked Registers): This creates the physical flip-flops that hold the "current_state". It only changes on the rising edge of the clock.
2. The Combinational Process (The Raw Wires/Gates): This calculates the "next_state" and the "outputs". It does not use a clock; it acts purely like an instant calculator made of copper traces and logic gates.

Here is what the complete VHDL looks like for both machines, side-by-side. Notice where the "external_input" is placed.

--- THE MOORE IMPLEMENTATION ---

-- 1. THE REGISTERS (Clocked)
process(clk)
begin
    if rising_edge(clk) then
        current_state <= next_state;
    end if;
end process;

-- 2. THE COMBINATIONAL LOGIC (Unclocked)
process(current_state, external_input)
begin
    -- Calculate next state
    case current_state is
        when STATE_IDLE => 
            if external_input = '1' then next_state <= STATE_TX;
            else next_state <= STATE_IDLE; end if;
    end case;
    
    -- Calculate Output (MOORE: Input is NOT in this sensitivity list!)
    case current_state is
        when STATE_IDLE => ready <= '0';
        when STATE_TX   => ready <= '1';
    end case;
end process;

--- THE MEALY IMPLEMENTATION ---

-- 1. THE REGISTERS (Clocked - Exactly the same as Moore!)
process(clk)
begin
    if rising_edge(clk) then
        current_state <= next_state;
    end if;
end process;

-- 2. THE COMBINATIONAL LOGIC (Unclocked)
process(current_state, external_input)
begin
    -- Calculate next state
    case current_state is
        when STATE_IDLE => 
            if external_input = '1' then next_state <= STATE_TX;
            else next_state <= STATE_IDLE; end if;
    end case;
    
    -- Calculate Output (MEALY: Input directly determines output)
    case current_state is
        when STATE_IDLE => 
            if external_input = '1' then 
                ready <= '1'; -- <--- IMMEDIATE PASS-THROUGH!
            else 
                ready <= '0';
            end if;
        when STATE_TX => ready <= '1';
    end case;
end process;

How Immediate Propagation Happens on Silicon
--------------------------------------------
In VHDL, any process that does not check for "rising_edge(clk)" synthesizes down to pure combinational logic (an unclocked network of LUTs and copper wires).

Let's trace a physical electrical signal through the Mealy machine while the system is sitting in "STATE_IDLE":

1. The FPGA is in STATE_IDLE. The physical flip-flops holding "current_state" are outputting the binary code for IDLE. This voltage is static and holding.
2. The "ready" output line is currently at 0V (logic low).
3. Suddenly, halfway through the clock cycle (nowhere near a clock edge), an external chip drives the "external_input" pin to 3.3V (logic high).
4. Because the "external_input" wire connects directly to an internal AND/OR gate (or LUT) that determines the "ready" signal, the electrons propagate through that gate at the speed of light.
5. Result: The "ready" pin flips to 3.3V just a few nanoseconds (the propagation delay of the gate) after the input changed. The FPGA did not wait for the clock.

If this were a Moore machine, the "external_input" wire would only connect to the gates calculating "next_state". The "ready" output logic would only be looking at the "current_state" flip-flops. Therefore, when the input changed halfway through the clock cycle, the "ready" pin would stay completely dead at 0V until the next clock edge actually latched that input into the state registers.

The VHDL "Sensitivity List" Hint
In the unclocked process header: "process(current_state, external_input)" The variables inside the parentheses form the sensitivity list. In hardware simulation, this tells the simulator: "If either of these voltages changes by even a fraction of a millivolt, instantly recalculate the outputs right now." In a Mealy machine, because "external_input" is in that list and directly drives the "ready" assignment, the output is structurally hardwired to the input.

Here is how that exact same architectural behavior maps to SystemVerilog.

SystemVerilog modernizes standard Verilog by introducing dedicated procedural blocks ("always_ff" and "always_comb") that explicitly tell the compiler your structural intent, making it much harder to accidentally synthesize wrong hardware.

1. The Moore FSM in SystemVerilog
--------------------------------
module moore_fsm (
    input  logic clk,
    input  logic reset,
    input  logic external_input,
    output logic ready
);

    // Define states using an enumerated type
    typedef enum logic {
        STATE_IDLE = 1'b0,
        STATE_TX   = 1'b1
    } state_t;

    state_t current_state, next_state;

    // 1. THE REGISTERS (Sequential Logic)
    // always_ff guarantees the synthesis tool creates physical flip-flops
    always_ff @(posedge clk or posedge reset) begin
        if (reset) begin
            current_state <= STATE_IDLE;
        end else begin
            current_state <= next_state; // Latched on the clock edge
        end
    end

    // 2. THE COMBINATIONAL LOGIC (Next State & Outputs)
    // always_comb automatically creates a complete sensitivity list under the hood
    always_comb begin
        // Default assignments to prevent accidental latches
        next_state = current_state;
        ready      = 1'b0;

        case (current_state)
            STATE_IDLE: begin
                if (external_input) next_state = STATE_TX;
                else                next_state = STATE_IDLE;
                
                ready = 1'b0; // Output depends ONLY on being in IDLE
            end

            STATE_TX: begin
                next_state = STATE_IDLE;
                
                ready = 1'b1; // Output depends ONLY on being in TX
            end
        endcase
    end

endmodule


2. The Mealy FSM in SystemVerilog
---------------------------------
Notice how in the Mealy version, "external_input" directly gate-determines the value assigned to "ready" right inside the "STATE_IDLE" case block, creating that instant, unclocked physical copper path to the output pin.

module mealy_fsm (
    input  logic clk,
    input  logic reset,
    input  logic external_input,
    output logic ready
);

    typedef enum logic {
        STATE_IDLE = 1'b0,
        STATE_TX   = 1'b1
    } state_t;

    state_t current_state, next_state;

    // 1. THE REGISTERS (Identical to the Moore machine)
    always_ff @(posedge clk or posedge reset) begin
        if (reset) begin
            current_state <= STATE_IDLE;
        end else begin
            current_state <= next_state;
        end
    end

    // 2. THE COMBINATIONAL LOGIC (Immediate Pass-Through)
    always_comb begin
        next_state = current_state;
        ready      = 1'b0; // Default state

        case (current_state)
            STATE_IDLE: begin
                if (external_input) begin
                    next_state = STATE_TX;
                    ready      = 1'b1; // <--- IMMEDIATE PASS-THROUGH! 
                                       // If external_input changes halfway through the clock cycle, 
                                       // ready flips to 1 instantly without waiting for clk.
                end else begin
                    next_state = STATE_IDLE;
                    ready      = 1'b0;
                end
            end

            STATE_TX: begin
                next_state = STATE_IDLE;
                ready      = 1'b1; 
            end
        endcase
    end

endmodule

Key Differences to Spot for a Software Developer:
* "<=" vs "=": Inside always_ff, we use non-blocking assignments ("<="), which schedule the state updates to occur concurrently precisely on the clock edge (mimicking real flip-flop array updates). Inside always_comb, we use blocking assignments ("="), which execute sequentially exactly like line-by-line execution in a standard software script because it represents raw combinational gates propagating voltages.
* "always_comb": Unlik VHDL where you must explicitly write out the sensitivity list "process(current_state, external_input)", SystemVerilog's always_comb automatically looks at every variable read inside the block and builds the gate topology to respond to any of them instantly.

(no subject)

Jul. 1st, 2026 07:27 pm
cali4nickation: (fpga)
[personal profile] cali4nickation
To transition from the legacy "discrete logic gate" mentality of Floyd's Digital Fundamentals to modern, industry standard RTL (Register-Transfer Level) hardware design, you need a book that shifts your thinking from "wiring chips"to "describing concurrent hardware behavior."

In the real world, an HDL script is not software code executed sequentially; it is a text-based blueprint for generating physical logic inside an FPGA's silicon fabric (like look-up tables and flip-flops). Here is the unfiltered, professional ranking of your textbooks, sorted from the absolute best next-stage candidates down to the ones you can safely skip.

+------+------------------------------------------------------------------+
| Rank | Textbook | Why it Fits (or Fails) Your Goal |
+------+------------------------------------------------------------------+
| 1 | Digital System Design with FPGA | THE TOP PICK. Perfectly bridges the gap after Floyd. It handles both VHDL and Verilog concurrently, focuses heavily on modern tool flows (Vivado), and immediately shifts you into modern hardware layout concepts instead of 
academic theory. | by Cem Unsalan & Bora Tar
+------+------------------------------------------------------------------+
| 2 | FPGA Prototyping by VHDL Examples | THE GOLD STANDARD FOR INTUITION. Chu is legendary in university EE programs for teaching people how to write HDL that synthesizes efficiently into physical hardware. He explicitly warns against treating HDL like software. | by Pong P. Chu
+------+------------------------------------------------------------------+
| 3 | Digital Design and Computer Architecture: ARM Edition | PHENOMENAL, BUT SLIGHTLY OFF-TOPIC. An absolute masterpiece in modern EE programs that skips 7400-fluff entirely. However, its primary goal is teaching you how to design a CPU architecture inside an HDL, which might be broader. | by David Harris & Sarah Harris
+------+------------------------------------------------------------------+
| 4 | Digital Design: An Embedded Systems Approach using VHDL | SOLID RUNNER-UP. Very good at looking at digital logic through the lens of modern integrated systems rather than old discrete chips. Highly respected, though slightly less hands-on with vendor tools than Unsalan or Chu. | by Peter Ashenden
+------+------------------------------------------------------------------+
| 5 | The FPGA Programming Handbook | A PRACTITIONER'S GUIDE. Good for practical tool navigation and rapid project building, but text reviews note it lacks the structural academic foundation required to completely unlearn old gate habits. | by Frank Bruno
+------+------------------------------------------------------------------+
| 6 | Fundamentals of VHDL for FPGA Programming Using Vivado | TOO NICHE. Focuses heavily on the mechanics of the specific Vivado software interface rather than teaching the deep architectural mindset of digital system design. | by Majid Pakdel
+------+------------------------------------------------------------------+
| 7 | Fundamentals of Logic Design | REDUNDANT. A massive classic textbook, but it spends far too much time on pencil-and-paper minimization techniques (K-maps, Boolean proofs) that tools automate instantly today. It introduces HDL too late. | by Roth
+------+------------------------------------------------------------------+
| 8 | Digital Systems Design with FPGAs | OUTDATED / ACADEMIC. More specialized and lacks the modern, streamlined readability of Unsalan or Chu for someone looking for a fast, intuitive reality check on the current state of the art. | by Ion Grout
+------+------------------------------------------------------------------+

Why the Top 2 Stand Out:

1. Unsalan & Tar -- "Digital System Design with FPGA"
This book is arguably the most modern entry on your list. It doesn't waste time pretending you are going to wire up a breadboard. It explicitly details the anatomy of modern FPGAs (Configurable Logic Blocks, LUTs, Slices, and ClockManagement) and directly maps how lines of HDL translate to those physical structures. If you want a quick, clean look at the toolchains and code paradigms used today, start here.

2. Pong P. Chu -- "FPGA Prototyping by VHDL Examples"
If you struggle with the concept of "concurrency" (the fact that every line ofan HDL script runs simultaneously in hardware, unlike standard sequential C++ or Python), Chu is the antidote. His code examples are highly disciplined,teaching you clean template structures for combinational logic versus sequential logic. It is the book most likely to give you that "aha!" moment regarding how industrial digital systems are actually modeled.

If I were reviewing the previous list as a peer reviewer, my critique would be: "The original list overemphasizes vendor toolchains (Vivado) and VHDL/Verilog syntax, rather than the core cognitive shift from software-like text to spatial hardware structures." To provide a true, distinct alternative, we have to look through a different lens: Which book most aggressively and elegantly destroys the "7400-discrete-chip" and "sequential software loop" mentalities for a fast-tracked professional? Under that criterion, the alternative ranking completely shifts.

+------+------------------------------------------------------------------+
| Rank | Textbook | The Peer-Review Rationale |
+------+------------------------------------------------------------------+
| 1 | Digital Design and Computer Architecture: ARM Edition | PROMOTED TO #1. If the goal is to unlearn old logic paradigms and see how modern digital systems are built from scratch, this is the undisputed king of undergraduate EE. It treats HDL as a first-class citizen from the beginning. | by Harris & Harris                              
+------+------------------------------------------------------------------+
| 2 | Digital Design: An Embedded Systems Approach using VHDL | PROMOTED TO #2. Ashenden's unique thesis is that digital design is now fundamentally about integrating systems, not just building standalone glue logic. It focuses heavily on design methodologies and verification (testbenches). | by Peter Ashenden
+------+------------------------------------------------------------------+
| 3 | FPGA Prototyping by VHDL Examples | DEMOTED TO #3. While Chu is an unmatched workbook for writing synthesis-ready code, its structure can feel like a repetitive series of lab exercises. If you aren't actually coding each example, you miss a lot of its value. | by Pong P. Chu
+------+------------------------------------------------------------------+
| 4 | Digital System Design with FPGA | DEMOTED TO #4. In a structural review, this book can be criticized for being too tied to Xilinx/AMD Vivado step-by-step guides. If you want conceptual intuition rather than a software manual, it ranks lower. | by Cem Unsalan & Bora Tar
+------+------------------------------------------------------------------+
| 5 | The FPGA Programming Handbook | STAYS AT #5. Solid for a developer looking for a rapid, pragmatic overview of the ecosystem, but it assumes you already have a bit of hardware intuition. | by Frank Bruno
+------+------------------------------------------------------------------+
| 6 | Fundamentals of Logic Design | STAYS AT #6. Still too dense with 1980s pen-and-paper optimization math that the computer handles for you today. | by Roth
+------+------------------------------------------------------------------+
| 7 | Fundamentals of VHDL... Using Vivado | STAYS AT #7. Too narrow; feels more like an application note for a specific software IDE than a textbook on digital system design. | by Majid Pakdel
+------+------------------------------------------------------------------+
| 8 | Digital Systems Design with FPGAs | STAYS AT #8. Outdated pedagogy compared to the top contenders. | by Ion Grout
+------+------------------------------------------------------------------+

Why this Alternative Top 2 Wins on Pure Intuition:

1. Harris & Harris -- "Digital Design and Computer Architecture"
The genius of this book is how it structures your mental model. It starts with the absolute atom of modern computing (the transistor), scales it up to gates, immediately maps those gates to HDL, and then uses that HDL to build a functional ARM processor. It completely bypasses the middleman of "7400-series chips on a breadboard." It shows you exactly how real-world commercial chips are designed today in places like Apple, AMD, or NVIDIA.

2. Peter Ashenden -- "Digital Design: An Embedded Systems Approach"
Ashenden is highly respected because he recognizes that modern digital systems do not exist in a vacuum--they are almost always connected to a processor core, memories, and buses. Instead of teaching you how to build isolated counters or multiplexers over and over, he teaches you how hardware modules communicate with each other using modern design methodologies. It is incredibly efficient for a high-level software developer trying to understand the physical constraints of hardware.

Reading either of these massive textbooks cover-to-cover would drag you right back into the rigid, academic EE treadmill. Since you already understand standard logic fundamentals from Floyd, you can laser-focus on a few chapters to update your mental model. Here is the exact "surgical strike" reading plan to get maximum modern intuition with minimal time investment.

1. "Digital Design and Computer Architecture" (Harris & Harris)

Skip the introduction, math proofs, and the entire second half of the book (which focuses on writing assembly and building a processor).

Read only:
* Chapter 3: Sequential Logic Design (Sections 3.3 to 3.4)
- Why: This is where you unlearn software sequential thinking. It introduces the concept of the system clock and Synchronous Logic. Pay attention to how Finite State Machines (FSMs) work here; in FPGAs, almost every control system is an FSM running on a clock edge.
* Chapter 4: Hardware Description Languages (All)
- Why: This is the exact pivot point from Floyd to the real world. It presents VHDL and Verilog side-by-side. Look at how they use code to describe a physical multiplexer or flip-flop. Notice the absolute lack of 7400 chips.
* Appendix A: Digital System Implementation (Sections A.1 to A.3)
- Why: This section bridges the theoretical gate to the physical silicon. Section A.3 explains Programmable Logic (FPGAs), introducing Look-Up Tables (LUTs). This is critical because modern FPGAs don't actually contain physical AND/OR gates; they use tiny RAM cells configured as truth tables to simulate them.

2. "Digital Design: An Embedded Systems Approach using VHDL" (Ashenden)

Ashenden is excellent for understanding how separate hardware modules actually talk to one another in an industrial setting, rather than treating logic like isolated math puzzles.

Read only:
* Chapter 1: Introduction and Methodology
- Why: Section 1.2 introduces the modern Electronic Design Automation design flow: Design -> Synthesis -> Simulation -> Mapping. Understanding this sequence is crucial because, in software, your compiler creates machine code; in hardware, your synthesis tool creates a schematic of physical elements.
* Chapter 4: Sequential Basics
- Why: Read this alongside Harris Chapter 3. Ashenden does an incredible job demonstrating how to cleanly separate "combinational logic" (instantaneous math) from "sequential logic" (storage elements controlled by the clock) using VHDL.
* Chapter 6: Implementation Fabrics
- Why: This is a pure structural overview of what is happening inside the chip. It covers how a design gets physically routed through the silicon fabric of an FPGA and discusses real-world constraints like clock distribution
networks.

Summary of the "Mental Shift" to Look For: As you read these specific chapters, look out for the one concept that trips up every software developer: Concurrency. In Python or C++, lines of code execute one after the other. In an HDL script, every single block of code is a physical circuit running at the exact same time. When the clock strikes, thousands of flip-flops update simultaneously. These chapters are designed to give you that exact spatial mental model.

However, "The FPGA Programming Handbook" by Frank Bruno is a rare exception to the Packt rule. It is a solid book, but it is solid specifically because of who wrote it, not who published it.

Frank Bruno is a seasoned hardware engineer; he's an industry veteran. Because of his background, the book has a specific flavor: it is highly pragmatic, toolchain-heavy, and project-focused. Here is an honest breakdown of whether it's worth your commute time or if it's too watered down:

Where it succeeds (Why it's a good commute read):
* It deals with the actual plumbing: While academic books love to show you beautifully clean code snippets in isolation, Bruno forces you to deal with the ugly reality of modern toolchains (Xilinx Vivado/Vitis). He covers modern industry standards that academics often ignore, like AXI buses (the standard interconnect protocol used to stitch hardware modules together in the real world) and memory controllers.
* Dual HDL coverage: He presents VHDL and SystemVerilog side-by-side. Seeing the same hardware concept described in both flavors is great for building rapid, high-level structural intuition.
* The "MicroBlaze" chapter: He covers how to instantiate a soft-core processor inside the FPGA fabric. This is peak modern design reality: you don't build everything from scratch out of gates; you drop a CPU into the silicon and use C to handle the slow stuff while using custom HDL modules for the fast stuff.

Where it falls short (The "Packt" influence):
* It mimics software development too closely: This is where the book risks catering a bit too much to the software crowd. It follows a "let's build a project" structure (LEDs -> Buttons -> Calculator -> VGA display). If you are just reading it on a train without a development board in front of you, a lot of the text reads like step-by-step instructions on clicking buttons in an IDE or debugging physical board pin assignments.
* Lacks deep structural theory: It will not give you the profound architectural "aha!" moment regarding silicon structures that Harris & Harris or Chu provides. It skips over deep discussions on timing closure, clock domain crossing, and how the synthesis engine maps text to physical Look-Up Tables (LUTs).

The Verdict for Your Commute: Keep reading it to kill time. Because you come from a professional software background, you will easily look past the syntax and appreciate the system architecture he's building (especially when he gets into pipelining, math optimization, and AXI streams).

Think of it as a "Day in the Life of a Xilinx Designer" field guide. It won't replace the deep foundational shifts you'll get from the specific chapters of Harris & Harris, but it provides excellent, gritty context for what real-world FPGA deployment actually looks like.

(no subject)

Jun. 30th, 2026 04:58 pm
cali4nickation: (Default)
[personal profile] cali4nickation
People are retarded.
Everything you see is fake.
Politics and justice are for those who
want to accrue unjust power over others.
Females must be put under control
or they'll destroy civilization.

Я абсолютно серьезно считаю что предсказать будет ли хуже лет через 10-20 в Москве или Америке нельзя считать самоочевидным. Я видел несколько радикальнейших изменений в рашкостане за лично мою жизнь. Включая к лучшему как в 90е. Здесь дела намного медленнее но и намного более неуклонно катятся в пропасть сколько я их наблюдаю. После 2020 дно пробилось окончательно и больше уже никогда даже иллюзии населенцам не давали. 

Очень может быть что всем хорошим Белым людям собраться и убить всех плохих браун пипл уже чисто физически слишком поздно. Без нищеты, без комиссаров, без жуткого климата, без революций, без мировых войн на своей территории. Просто пара диаспор захватила власть и поураганила поколение-другое. По одной шестой мы видим что жизнь на этом не закончится еще десятки лет но никакого возврата к нормальности уже не будет если нет членского билета айпака или ануса развальцованного Ниггером на ближайшем DEI параде.  

Ирония в том что не свалить с родины уродины тоже было бы не выходом. Catch 22. Я сжег свой скромный потенциал на не пойми что. Таким трудом и такой ценой добытый паспорт уже сейчас разбрасывают с вертолетов любому смуглому дебилу со всей его криминальной родней. Как подтвердил сегодня один Суприм фуд Корт закон что дышло везде где есть начальство и засунут это дышло тебе лично, $USERNAME.

Press Release – June 30, 2026

Jun. 30th, 2026 08:09 pm
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Posted by SFWA Communications

Image

Looking Back and Moving Forward

Dear writer, 

We’ve had an incredible year at SFWA. We charted new Constellations and visited a Quasar on our professional journey to the latest Nebulas. Together, we expanded our orbit, welcomed new travelers, and built momentum that will carry us toward our next horizon.

Yet, we can’t move forward without looking back. This year, we lost Past President Jane Yolen. A Grand Master, storyteller, and tireless advocate for writers, she inspired a generation of writers (like me!) to keep writing, creating, and, most importantly, imagining. Her legacy lives on, not just in the stories and poems she wrote, but in the community she helped shape. In the months and years ahead, we will continue to honor Jane by celebrating her work and carrying forward the spirit of generosity that defines her legacy. (or defined her life?)

Our community was joined this year by Executive Director Isis Asare. During her tenure, SFWA reached new audiences, launched ambitious initiatives, strengthened current programming, and became decidedly and emphatically more human. As Isis concludes her time at SFWA, we are deeply grateful for her collaborative leadership and supportive vision of what our community can and should be. We will miss her steady hand, but we also know that her next chapter will continue to shape the future of our genre. We will be cheering her on for years to come. You can follow along with Isis’ journey here.

As one chapter closes, another begins. At this year’s Nebulas, we welcomed N. K. Jemisin as SFWA’s newest Grand Master, celebrating her groundbreaking and world-shaking contributions to speculative fiction. In her acceptance speech (which literally lit the room on fire), she reminded us of the collective power and possibility of our community: “We should revel in our growth, fellow writers. And as we grow, we can make the world better, too.” That spirit has always been the gravity that holds SFWA’s constellation together. We are a community of creators who challenge the boundaries of what is possible, and build, build, build the future we want to see (revising all along the way). 

This August, at Worldcon, we’ll continue that tradition by honoring our next Grand Master, another writer whose work has expanded our universe and strengthened our community. I can’t wait to introduce you to the next star in our bright sky.

The future of our genre has never been built by one writer, one organizer, or one creator. It is shaped by the networks, community, uplift, and care that help us keep creating. After all, a constellation is only as bright as all of the stars reflecting light within it. With that in mind, this summer, SFWA is opening new opportunities and strengthening pathways for care and connection with the launch of our Writers in Crisis Grant on August 1 and the opening of our Givers Fund Grant on September 15. 

These programs are a promise to our community in a time of change: when you are struggling or facing moments of uncertainty, and when you are ready to build something bigger and better than what was there before, SFWA will be there for you with practical support, a helping hand, and a big reminder that none of us has to go it alone. As Jemisin reminded us, we can combine our powers, and as Grand Master Nicola Griffith told us in her 2025 speech, “No one does this alone.” Together, we can care for one another as we reach for the stars and build the future we want to see (with magic, science, sorcery, monsters and miracles). There is always more on the next horizon. 

Speaking of which, Singularity returns next Tuesday, with new Recommended Reading List features and new pro-human guidance from our Emerging Tech committee, along with updates from other great teams, SFWA members, and industry peers. If you are an active SFWA member, you can also join Emerging Tech for an introductory session this July 5 at 8 a.m. PDT (or review the panel on our new SFWA Events Theater at your leisure later).

The universe of SFWA is still expanding. As we continue this journey together (always), we want you to know this: wherever you are at in your writing, in the world, or with whatever challenges you are facing, SFWA is here for you because of you. 

So, keep creating,

Kate Ristau

SFWA Board President

The post Press Release – June 30, 2026 appeared first on SFWA - The Science Fiction & Fantasy Writers Association.

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Posted by Planetside Crew

by Aashima Rawal

Series banner for Writing from History with Planetside logo
Read by Liz J. Bradley

A child stands before a Bright Door carved into the cracked walls of a city that always braces for impact. Police lines shimmer like heat across streets split by old debts. On one side, jinn watch with quiet, tired defiance. On the other, a clerk posts notices about vanished neighborhoods. Beyond the threshold, the architecture folds in on itself and reforms, as if memory is the only true map. In  Vajra Chandrasekera’s The Saint of Bright Doors, borders are drawn not with ink but with ghosts. The empire collapses again, but this time in the imagination of someone who refuses to accept the old version of the story.

Ornate doorway leading into a yellow courtyard
Bright Door. Photo by Tekeshwar Singh on Unsplash.

Speculative fiction from former colonies often doesn’t prioritize spectacle. Its urgency lies elsewhere. These stories rebuild what history tried to erase. They confront the past without allowing it to dictate the ending. In the hands of a growing group of South Asian writers, the project becomes something quieter and far more ambitious: a way of restoring dignity to the record.

Decolonial speculative fiction has gained traction over the years, but it has recently become hard to ignore. Chandrasekera’s Rakesfall won the 2025 Ursula K. Le Guin Prize for Fiction for its ability to connect hope to the aftershocks of colonial violence. Writers like Premee Mohamed and Sami Shah consistently appear on the Nebula, Locus, and Le Guin Prize lists. Their work is recognized not for niche appeal but for expanding the emotional reach of the field. Many describe their stories as a form of repair—a conversation with parts of history that were rushed or redacted. Their rise also reveals familiar tensions like the so-called Tiffany Problem, where historically accurate names or customs in non-Western settings are deemed “incorrect” simply because they fall outside Eurocentric expectations. This serves as a reminder that imagination also has borders, and someone has to redraw them.

Rewriting the empire on the page isn’t just a matter of rearranging events. It involves method. How do you acknowledge wounds without reopening them? How do you write about power clearly instead of imitating it? The stories in the anthology The Djinn Falls in Love and Other Stories offer one approach. Jinn are not depicted as curiosities or exotic ornaments. They are figures carrying memory, burden, and rebellion. In Kamila Shamsie’s contribution, jinn move through domestic and communal spaces rather than distant myth, grounding the supernatural in the everyday aftermath of loss. Amal el-Mohtar’s story similarly resists spectacle, using lyric restraint and intimate perspective to explore longing and fracture instead of grand conflict. In both cases, folklore becomes a vehicle for emotional complexity rather than a simplified symbol.

Premee Mohamed has discussed drawing on scientific research, including climate science, in her speculative fiction, while still foregrounding community, character, and emotional stakes. Tasha Suri has said that the world of Empire of Sand was heavily inspired by the Mughal Empire and that she drew on the culture and politics of Mughal India before deliberately diverging from historical context to meet the needs of the plot. Critics describe the future Tel Aviv and Jaffa setting of Central Station as a liminal, layered border city and hub of cultural exchange, where multiple histories, faiths, and communities intersect in everyday life rather than through explicit political exposition. Taken together, these examples suggest a model of ethical alt-history rooted in attention and care rather than entitlement to historical material.

To rewrite an empire is to ask what might have happened if the world had been kinder, and then to sit with the knowledge that it wasn’t. It is both an act of mourning and imagination. Sami Shah’s “Reap” takes this to its limits. Partition, the 1947 division of British India into India and Pakistan, triggered mass displacement and violence that still shapes family memory across the region. In Shah’s story, the jinn bear witness to what people cannot bear to name, moving through the aftermath with a steadiness that feels like endurance. The story unsettles because it will not allow easy distance. Mohamed explores this same instinct in her essays: the inheritance of grief and the responsibility to transform it into something usable. This image recalls textile traditions like khadi and kantha, the way one carries the mark of the hand, while the other layers scraps of past lives into a single surface. Memory, in both cloth and story, rarely follows a straight line. It accumulates.

White kantha embroidery with colorful animals, including elephants, birds, and deer.
Kantha embroidery. Image by Nancy Kassim Farran from Pixabay.

For writers, this shift in speculative fiction is not a trend but a change in approach. It calls for slower reflection. It calls for empathy instead of spectacle. Recent Planetside craft columns state it clearly: use archives, not assumptions; write with history, not over it; let care shape the revision. The goal is not to tidy up the past but to listen to it. This might involve returning to primary documents, noting who is missing from official maps, or paying attention to rituals that continue to hold stories long after the paperwork has disappeared.

Each time a writer reimagines the empire, the world gains another map—one that accepts complexity, sorrow, and resilience. In Chandrasekera’s city of Bright Doors, no border is permanent. Streets erased by policy can be brought back into existence by memory alone. South Asian speculative fiction takes this possibility seriously. It offers a way to write with both accuracy and humanity, treating history not as a fixed monument but as something still capable of change.

Explore more articles from Writing from History

Author photo of Aashima RawalAashima Rawal is a freelance writer with bylines in Art UK, Monograph, Hearth Magazine, Modest, and Business Insider. She writes about the intersections of storytelling, history, and culture, blending research with an accessible, reflective style. Her work often explores how memory, craft, and imagination shape the worlds we inherit and the ones we build.

The post Rewriting the Empire: Lessons from South Asian Speculative Fiction appeared first on SFWA - The Science Fiction & Fantasy Writers Association.

(no subject)

Jun. 28th, 2026 01:07 pm
cali4nickation: (fpga)
[personal profile] cali4nickation
ROBOTICS & EMBEDDED SYSTEMS DEVELOPMENT LEARNING PATHWAY

MODULE 1: BROAD AREA OVERVIEW & PARADIGM SHIFTS

Robotics sits at the intersection of mechanical engineering, electrical engineering, and computer science. When looking at the spectrum of tools—from a $5 Arduino to a high-end FPGA, or from bare-metal C to ROS2—it can feel like a massive jigsaw puzzle.

1. THE HARDWARE PROGRESSION: ARDUINO -> RASPBERRY PI -> FPGA
Think of this progression not just as "getting more powerful," but as moving from strict hardware control to heavy computational data processing, and finally to custom hardware architecture.

[ Arduino / Microcontrollers ] --> Lower-level, deterministic, hardware-facing (Sensors/Actuators)


[ Raspberry Pi / SBCs ] --> Higher-level, asynchronous, data-heavy (Vision, ROS2, Networking)


[ FPGAs / Custom Silicon ] --> Ultra-low latency, parallel processing (High-speed DSP, Safety-critical)

* Tier 1: Microcontrollers (Arduino, STM32, ESP32)
Single-core processors running "bare metal" code (no operating system) or a lightweight Real-Time Operating System (RTOS). They interact directly with the physical world, reading analog voltages and generating PWM signals in deterministic, real-time loops.

* Tier 2: Single Board Computers / SBCs (Raspberry Pi, Jetson Nano)
Full computers running a Linux operating system. They handle the "brains" of a complex robot: computer vision (OpenCV), path planning, and running ROS/ROS2. Because Linux is asynchronous, SBCs are usually paired with a microcontroller for real-time timing.

* Tier 3: FPGAs (Field Programmable Gate Arrays)
Blank slates of silicon hardware. You rewrite the physical hardware circuitry using Hardware Description Languages (Verilog/VHDL). Used where microcontrollers are too slow and SBCs are too erratic (e.g., high-speed vision, aerospace, custom sensor fusion).

2. SOFTWARE & ECOSYSTEMS: CUTTING THROUGH THE NOISE
* Embedded C/C++: Still the undisputed king of industrial and production robotics. It compiles directly to machine code, has zero overhead, and gives you absolute control over memory and hardware registers.
* MicroPython: Excellent for rapid prototyping, hobbyists, and quick testing, but rarely used in production industrial automation due to a lack of speed and tight memory management.
* ROS vs. ROS2 (Robot Operating System): ROS is a middleware framework providing standard message-passing between robot components. ROS 1 is dead/dying; ROS2 is the modern industry standard for complex autonomous systems (AGVs, AMRs, advanced robotic arms).

3. PROFESSIONAL RELEVANCE: WHERE DO YOU WANT TO LAND?

| Path                              | Typical Work                            | Core Tech Stack
+-----------------------------------+-----------------------------------------+-------------------------------
| Industrial Automation / Integrator| Factory automation, field commissioning | PLCs (Allen-Bradley, Siemens), Industrial Robotic Arms (FANUC, KUKA), basic C. |
| Mechatronics / Lab Technician     | R&D labs, prototyping, test fixtures    | Microcontrollers (Arduino, STM32), C/C++, basic PCB design, 3D printing. |
| Advanced Autonomous Systems       |Self-driving cars, warehouse AMRs, drones| Linux, ROS2, C++, Python, Edge AI hardware (Nvidia Jetson). |

MODULE 2: STRATEGIC PROGRESSION FOR SOFTWARE ENGINEERS

Given deep software engineering expertise and an EE background, treating an 8-bit Arduino Uno as a final destination would feel like playing with a toy. The simplified "Arduino language" abstraction hides memory, registers, and interrupts.
A high-level software background paired with digital logic courses allows skipping the "how to write a loop" phase and moving straight into concurrent execution, memory mapping, and timing constraints.

1. THE REAL-WORLD HARDWARE & SOFTWARE SPECTRUM
* Tier 1: Advanced Microcontrollers (STM32, ESP32, RP2040)
Programming these professionally means bypassing the Arduino IDE entirely. You use standard Embedded C/C++ with a vendor HAL (Hardware Abstraction Layer) or write directly to registers, handling asynchronous hardware interrupts and FreeRTOS thread priorities.

* Tier 2: Single-Board Computers & Embedded Linux (Raspberry Pi, Jetson)
This tier deals with writing multi-threaded C++ or Python applications, optimizing systems via Linux kernel tweaks (or real-time patches like PREEMPT_RT), managing IPC (Inter-Process Communication), and deploying ROS2 middleware layers.

* Tier 3: Digital Hardware & FPGAs (Basys 3, Artix-7)
Using Verilog or VHDL to define physical digital circuits—multiplexers, registers, state machines, and ALUs. Invaluable if optimizing defense/aerospace sensor arrays or software-defined radio (SDR) platforms where software execution is too slow.

2. THE GOLDEN THREAD: AN ADVANCED ROBOTICS CAR KIT
A robotic car kit powered by a Raspberry Pi serves as a miniature version of a production autonomous vehicle system, forcing the integration of the exact architectural layers encountered in modern industry:
* The Low-Level Layer (Microcontroller): Handles tight, high-frequency, real-time control loops: reading optical wheel encoders, calculating PID variables, and driving PWM signals to the motors to maintain a precise trajectory.
* The High-Level Layer (Raspberry Pi): Handles compute-heavy tasks like capturing data from a camera or LiDAR, processing images via OpenCV, and executing path-finding algorithms.
* The Bridge (IPC / ROS2): Communication loop between the Pi (brain) and motor controller (nervous system) via UART, I2C, or SPI, mapping distinct software nodes communicating cleanly across a unified system.

MODULE 3: HARDWARE PLATFORMS & RASPBERRY PI CONFIGURATIONS

A professional development platform uses a split-controller architecture: a Raspberry Pi as the "host" brain running a high-level asynchronous environment (Linux/ROS2) alongside a secondary real-time co-processor (ESP32/STM32) handling low-level constraints.

1. ARCHITECTURAL PLATFORMS
* Mid-Range Tier ($90 - $150): Focuses on computer vision and processing camera telemetry frames in real-time while issuing drive commands (e.g., SunFounder PiCar-X architecture).
* Advanced Tier ($300 - $400): Features Time-of-Flight (TOF) LiDAR arrays, closed-loop encoder motors, and Mecanum wheels for 360° omnidirectional movement, introducing kinematic transformation matrices and SLAM mapping under ROS2 Humble.

2. RASPBERRY PI 5 CONFIGURATIONS & PITFALLS
* The RAM Dilemma (4GB vs. 8GB): 4GB handles standard ROS2 middleware, classical computer vision, and kinematics. 8GB is mandatory for on-device compilation of large C++ packages (MoveIt!, OpenCV) without compiler crashes, edge AI neural networks, and 3D SLAM point clouds.
* Pitfall A: The 5V / 5A Power Delivery Trap: Pi 5 requires a 5V/5A (25W) power profile. Cheap kits designed for Pi 4 (5V/3A) will limit current to USB ports down to 600mA, causing voltage drops, CPU throttling, or kernel panics when motors or LiDAR spin up.
* Pitfall B: RP1 Southbridge & Peripheral Libraries: Pi 5 offloads peripheral management (GPIO, I2C, SPI) to an internal RP1 chip. Legacy Python libraries like RPi.GPIO do not work. Ensure kits target Debian Bookworm and use modern frameworks like gpiod.
* Pitfall C: Thermal Throttling: The Pi 5 runs significantly hotter than its predecessors. Ensure the kit's physical architecture leaves enough clearance to mount the official Raspberry Pi Active Cooler fan/heatsink assembly.

MODULE 4: MOBILE MANIPULATORS & BALANCING BUNDLES

A mobile manipulator (a wheeled robot with a multi-axis arm mounted on it) moves engineering complexity into simultaneous 3D kinematics, shifting centers of gravity, and serial bus communication overhead.

1. CRITICAL DESIGN PITFALLS TO AVOID
* Shifting Center of Gravity: When a 5-Degree-of-Freedom (5DOF) arm extends forward, the weight distribution shifts instantly. Avoid cheap plastic; look for a heavy aluminum alloy chassis with a wide, low-profile footprint.
* Bus Servos vs. PWM Servos: Do not buy kits using cheap 3-pin PWM hobby servos. For trajectory planning, you need Serial Bus Servos (UART, RS-485, or TTL) that pipe telemetry back—including current angle position, temperature, voltage, and load.
* Kinematic Incompatibility: Ensure the platform natively supports MoveIt! 2 (the ROS2 framework for arm trajectory planning and collision avoidance) and provides a valid URDF (Unified Robot Description Format) model.

2. BUNDLE (PI INCLUDED) VS. BRING YOUR OWN PI

| Factor                    | Bundle (Pi Included)                                     | Bring Your Own Pi |
+---------------------------+--------------------------------------------------------------
| Hardware Cost             | Higher (Includes manufacturer hardware markup).          | Lower (Buy components at true retail distribution price). |
| Time to First Line of Code| Fast. Ships with pre-compiled OS images/ROS2 spaces.     | Slow. Sourcing, flashing OS, cloning repos, configuring drivers. |
| Educational Value         | Focuses immediately on high-level robotics math/control. | Forces mastery of low-level Linux deployment and dependency fixing. |
| Long-Term Flexibility     | Can feel limiting if the pre-baked image is locked down. | Ultimate freedom to update packages or swap the Pi to other tasks. |


MODULE 5: THE CONCEPTUAL-FIRST PATHWAY & MODERN TEXTBOOKS

In modern robotics software engineering, the physical hardware is often treated as an implementation detail. You do not need a physical kit to analyze architectural abstractions; 90% of trajectory planning can be performed inside 3D simulators like Gazebo.

1. DATA FLOW IN SIMULATION DISCIPLINES
[ Your Navigation/Trajectory Code ] ───► (Standard ROS2 Messages / Topics) ───► [ Gazebo 3D Simulator ] ───► Simulates LiDAR, joint torques, and camera frames.

2. THE TRUTH ABOUT LANGUAGE DOMINANCE: C++ VS. PYTHON
ROS2 is not synonymous with Python. In commercial robotics, C++ is the undisputed king of production, while Python is used as architectural glue.
* Where C++ Dominates: Real-time control loops (ros2_control executing at 100Hz-500Hz without Garbage Collection latency spikes), high-throughput data pipelines (LiDAR point-cloud manipulation), and deterministic multi-threaded executors pinned to specific CPU cores.
* Where Python Dominates: System orchestration (all ROS2 launch scripts are Python), rapid prototyping of mathematical models, and AI/ML pipelines (wrappers for PyTorch/TensorFlow).
* The Architectural Secret: The core ROS2 client library layer (rcl) is written in pure C. Because the C++ library (rclcpp) and Python library (rclpy) wrap the same underlying C code, a C++ node can communicate with a Python node seamlessly over network sockets.

3. TEN MODERN TEXTBOOKS FOR EXPERIENCED DEVELOPERS

PART A: ROS2 & ARCHITECTURAL MIDDLEWARE
* 1. "Programming Robots with ROS 2: BYO Robotic System" (Morgan Quigley, Brian Gerkey, & William D. Smart)
The modern blueprint for distributed robotics software. Details graph structures, lifecycle nodes, and asynchronous message-passing configurations using C++ and Python.
* 2. "Mastering ROS 2 for Robotics Programming (4th Edition)" (Lentin Joseph & Dr. Jonathan Cacace)
Explicitly targeted at C++ engineers. Covers real-time plugins for ros2_control, multi-threaded executors, MoveIt! 2, and node composition containers.
* 3. "ROS 2 Cookbook" (Jonathan Cacace)
Structured as an advanced recipe book using pure C++. Focuses on zero-copy message passing via shared pointer memory and real-time memory-mapped sensor buffering.
* 4. "Mastering Autonomous Robotics with ROS2 and Python" (Wilson Hayes)
Focused on high-level pythonic architecture. Explains how to inherit from rclpy.node.Node and manage asynchronous execution using callback executors.
* 5. "Learn Robotics Programming (3rd Edition)" (Danny Staple)
Teaches software engineering best practices within robotics: structured configuration files, unit testing, and modular driver abstractions under Linux.

PART B: SPATIAL NAVIGATION, MATRICES & KINEMATICS
* 6. "Probabilistic Robotics" (Sebastian Thrun, Wolfram Burgard, & Dieter Fox)
The world-standard reference for autonomous vehicle tracking. Covers state-estimation equations, Extended Kalman Filters (EKF), Particle Filters, and SLAM math.
* 7. "Modern Robotics: Mechanics, Planning, and Control" (Kevin M. Lynch & Frank C. Park)
Covers multi-joint arms and mobile base kinematics using screw theory and Lie groups. Supported by an open-source, production-ready pure C++ library on GitHub.
* 8. "Robotics, Vision and Control: Fundamental Algorithms in Python" (Peter Corke)
Unifies navigation, computer vision transforms, and kinematics loops. Highly programmatic; every chart and equation matches lines of executable code.
* 9. "Hands-On SLAM for Autonomous Vehicles with C++" (Dr. Elias Baran)
Pure C++ execution using the Eigen Matrix Library to process high-throughput 3D LiDAR point clouds and IMU data under strict millisecond timing constraints.

PART C: CONTROL THEORY & HARDWARE INTERFACING
* 10. "Embedded Systems: Real-Time Interfacing to ARM Cortex-M Microcontrollers" (Jonathan Valvano)
The ultimate manual for the machine's "nervous system." Focuses on hardware interrupts, DMA channels, SPI/I2C drivers, and writing custom RTOS schedulers in C/C++.

(no subject)

Jun. 27th, 2026 01:00 pm
cali4nickation: (fpga)
[personal profile] cali4nickation
--------------------------------------------------------------------------------
SECTION 1: THE ORIGINS OF SHIFT REGISTERS AND COUNTERS
--------------------------------------------------------------------------------

Were they a natural next level after the D Flip-Flop? Yes, but with a fascinating historical twist: the concept of the shift register actually predates the standard semiconductor D-type flip-flop. Before the silicon D-flip-flop (like the classic 7474 IC) became the industry standard, early computers in the 1940s and 1950s used vacuum tubes, delay lines, and magnetic core memory.

* The Pioneer: An Wang (founder of Wang Laboratories) co-invented the magnetic pulse controlling device in the late 1940s, which was essentially a magnetic core shift register. It was crucial because early computers processed data serially (one bit at a time) to save on the massive cost and size of vacuum tubes.
* The Logic Leap: Once the transistor arrived and discrete flip-flops (initially J-K flip-flops, and later D-type) were standardized in the 1960s, cascading them became the obvious next step.

If a single D-flip-flop passes its data from D to Q on a clock edge, stringing the Q of one into the D of the next creates a digital conveyor belt.

          +---+        +---+        +---+
  Data -->| D |------->| D |------->| D |---> Serial Out
          |   |Q       |   |Q       |   |Q
  Clk  -->|>  |    +-->|>  |    +-->|>  |
          +---+    |   +---+    |   +---+
            |      |     |      |     |
            +------+-----+------+-----+---- Clock Line

Counters followed the exact same logical progression. By feeding the inverted output (~Q) of a flip-flop back into its own D input, you create a divide-by-2 toggle. Chain those together, and you have a binary ripple counter. They were the absolute natural progression because, without them, a flip-flop is just a single isolated cell of amnesia-curing memory; with them, you have computation and time tracking.

--------------------------------------------------------------------------------
SECTION 2: ARCHITECTURAL EVOLUTION
--------------------------------------------------------------------------------

Did they change much once invented? Architecturally? No. Restructured for performance? Massively. The foundational logic of a shift register or a synchronous counter hasn't changed since the mid-20th century. A 4-bit bidirectional shift register with parallel load (like the historic TTL 74194 IC) operates on the exact same state table as a shift register module written in SystemVerilog today.

However, they underwent massive internal changes to overcome physical limitations:

* Asynchronous to Synchronous: Early counters were "ripple counters" (asynchronous), where the output of one flip-flop clocked the next. This caused a cascading delay (propagation delay), leading to temporary false readings ("glitches") during transitions. The industry quickly shifted to synchronous counters, where a single global clock hits every flip-flop simultaneously, and look-ahead carry logic determines the next state.
* Silicon Topology: In early integrated circuits (ICs), transistors were precious. Shift registers changed from static architectures (holding data indefinitely) to dynamic layouts (using parasitic capacitance to temporarily store bits, requiring a continuous clock) to save space in early microprocessors, before settling back into high-speed static CMOS designs.


--------------------------------------------------------------------------------
SECTION 3: THE MODERN FPGA & HDL WORLD
--------------------------------------------------------------------------------

Are these abstractions still valid in the HDL/FPGA world? Absolutely. They are fundamental building blocks of hardware description languages (HDLs), though the way you implement them has evolved from picking chips off a shelf to describing behavior.

Behavioral Inferencing (The Modern Way)
---------------------------------------
In Vivado or Quartus, you rarely instantiate a specific "counter component" from a library anymore. Instead, you write behavioral code. The synthesis tool is smart enough to look at your math and infer the optimal hardware structure.

Example of a counter in SystemVerilog:

always_ff @(posedge clk or posedge rst) begin
if (rst)
count <= 0;
else
count <= count + 1; // The tool infers a synchronous counter with look-ahead carry
end

Are they built into standard component libraries?
-------------------------------------------------
Yes, but they exist at two distinct layers inside tools like Xilinx Vivado:

Layer 1: Architecture-Specific Primitives (The Silicon Level) Xilinx FPGAs don't actually build shift registers out of standard flip-flops if they can avoid it. They use a brilliant hardware trick called SRL (Shift Register LUT). A standard 6-input Look-Up Table (LUT) inside a Xilinx Configurable Logic Block (CLB) can be configured to act as a 32-bit shift register *without using a single discrete flip-flop*. If you need a shift register, Vivado will map your HDL code directly to these SRL16E or SRL32E primitives because it saves massive amounts of silicon real estate.

Layer 2: IP Catalog Modules (The Macros)
If you open Vivado's IP Catalog, you will find dedicated, highly optimized macros:
* Binary Counter IP: A customizable core where you can GUI-configure bit width, increment value, set/clear behavior, and clock enables. Vivado optimizes this core down to the dedicated carry chain logic (CARRY4 or CARRY8 primitives) embedded next to the LUTs for ultra-fast arithmetic.
* RAM-based Shift Register IP: For massive delay lines (like video line buffers), utilizing the FPGA's Block RAM (BRAM) or Distributed RAM rather than discrete registers.

--------------------------------------------------------------------------------
SECTION 4: UNDERSTANDING DEVICE PRIMITIVES
--------------------------------------------------------------------------------

When you mention "SRL32E" and "CARRY8" primitives do you have a particular limited set of primitives in mind? Similar to how individual flip-flops or logic gates used to be?

Yes, exactly. Primitives belong to a highly specific, limited set of fundamental building blocks called Device Primitives. They are the modern silicon equivalent of the classic 7400-series TTL discrete logic gates, but instead of being packaged in plastic chips on a breadboard, they are the atomic-level hardwired structures etched directly into the FPGA silicon.

An FPGA looks like an infinite sea of programmable logic, but underneath, it is constructed from a strict, finite library of hardwired silicon structures. A "primitive" is the lowest level of abstraction a designer can manipulate. You cannot break a primitive down into smaller components inside the software—it represents actual, unchangeable hardware layout.

For a modern Xilinx UltraScale+ architecture (which uses the CARRY8), the entire library of core logic primitives is relatively small—often numbering just a few dozen primary blocks that you use repeatedly.

Examples of Core Xilinx Primitives:
* FDRE / FDSE: The fundamental D-Flip-Flop (with Clock Enable and Sync Reset/Set).
* LUT6: A 6-input Look-Up Table (the basic truth-table evaluator).
* SRL32E: A 32-bit Shift Register using a single LUT's internal memory space.
* CARRY8: A dedicated 8-bit fast-carry lookahead cascade logic block used to speed up math.
* BRAM_EXP: A hard block of Random Access Memory.
* DSP48E2: A dedicated, hardwired Multiply-Accumulate math engine.

Cross-Manufacturer Portability
------------------------------
Conceptually? Yes. Atomically and Literally? No.

The underlying digital architectures across different FPGA vendors are remarkably similar because they face the exact same physics and mathematical constraints. However, the naming conventions, exact sizes, and silicon layouts are fiercely proprietary and vendor-specific.

The Vendor Equivalency Map:

+--------------------------+-----------------------+-----------------------+-----------------------+
| Function / Concept       | Xilinx (AMD)      | Intel (Altera)       | Lattice |
+--------------------------+-----------------------+-----------------------+-----------------------+
| Basic D-Flip-Flop        | FDRE              | dffe                 | IFS1P3DX   |
| Arithmetic Carry Block   | CARRY8 / CARRY4   | ALMSO / Carry Chains | CCU2 |
| LUT-based Shift Register | SRL16E / SRL32E   | MLAB / ALM Emulation | LUT4 (RAM mode) |
| Basic Logic Element      | CLB (Configurable | ALM (Adaptive Logic  | PFU (Programmable |
| | Logic Block) | Module) | Functional Unit)  |
+--------------------------+-----------------------+-----------------------+-----------------------+

Because primitives are vendor-specific, writing code that explicitly instantiates them makes your code unportable. To solve this, the industry uses two methods:

1. Inference (Preferred): You write plain, industry-standard behavioral math (A <= B + C). Vivado infers a CARRY8. Intel's Quartus compiler looks at the exact same line of code and infers an Intel ALM carry chain.
2. Structural Wrappers: If a developer absolutely must manually instantiate a primitive, they wrap it inside a generic conditional module:

module my_fast_counter ( input clk, input [7:0] d, output [7:0] q );
`if DEFINED_XILINX
CARRY8 xilinx_carry_inst (...);
`elsif DEFINED_INTEL
intel_carry_block intel_carry_inst (...);
`endif
endmodule


--------------------------------------------------------------------------------
SECTION 5: TEXTBOOKS VS. INDUSTRY REALITY
--------------------------------------------------------------------------------

What is the usual approach in modern EE textbooks? Do practicing HDL developers
think much about Device Primitives? Modern electrical and computer engineering (ECE) textbooks have largely shifted away from teaching discrete 7400-series TTL logic as a primary design methodology. Instead, they lead with HDLs (SystemVerilog/VHDL) and skip proprietary primitives in the main text to remain vendor-agnostic.

Textbooks introduce an intermediate, idealized abstraction:

+-------------------------------------------------------------+
| Ideal Logic Gates & K-Maps |
+-------------------------------------------------------------+
v
+-------------------------------------------------------------+
| Behavioral HDL (SystemVerilog/VHDL) |
+-------------------------------------------------------------+
v
+-------------------------------------------------------------+
| Generic Logic Element (Generic LUT + MUX + Programmable FF)|
+-------------------------------------------------------------+
v
+-------------------------------------------------------------+
| Proprietary Target Silicon (SRL32E, CARRY8, dffe, etc.) |
+-------------------------------------------------------------+

Do Practicing HDL Developers Care About Primitives?
---------------------------------------------------
For 90% to 95% of everyday development, practicing digital designers do not think about device primitives. They rely entirely on behavioral inference. Modern synthesis tools are incredibly sophisticated compilers. However, there is a crucial 5% exception where primitives are completely mandatory:

A. Clocking and Reset Infrastructure
FPGAs have dedicated, hardwired global clock routing networks. To use the on-chip Phase-Locked Loops (PLLs) or clock buffers, you must instantiate primitives like the Xilinx BUFG or MMCME4_ADV.

B. High-Speed I/O and Double Data Rate (DDR)
When interfacing with external pins at hundreds of megahertz, you need absolute control over setup and hold times right at the chip's physical boundary using IDDR or ODDR primitives.

C. Floorplanning and RPMs (Relationally Placed Modules)
When an FPGA design is packed to 90% capacity and failing to meet its timing constraints, designers use primitives to force the tool's hand, applying attributes that lock those components to precise X/Y coordinates on the silicon die.

The Mindset Summary:
Think of device primitives like inline assembly language in software engineering. A modern C++ or Rust developer trusts the compiler's optimization flags (-O3) to generate efficient machine code for standard loops and logic. You don't drop into assembly to write a basic counter. But if you are writing a low-level device driver or squeezing the absolute last drop of performance out of a cryptographic loop, you open up the assembly window. Primitives are the assembly language of the silicon world.

(no subject)

Jun. 26th, 2026 02:46 pm
cali4nickation: (Default)
[personal profile] cali4nickation
Always hang a traitor before you shoot an enemy.

"On Wednesday, the Texas State Board of Education voted to remove the American Revolution from 11th-grade U.S. History. The Battles of Lexington and Concord, the opening shots of the war that created this country, gone. In their place? Oprah Winfrey"

Революция отменяется а теперь дискотека. При аятолле хамини такого не было.

(no subject)

Jun. 26th, 2026 01:41 pm
cali4nickation: (fpga)
[personal profile] cali4nickation
The evolution of flip-flops is a fascinating intersection of mid-century logical abstraction, chemical physical engineering constraints, and naming quirks that have survived into the 2020s. Here is the breakdown of how these fundamental storage elements came to be, why they have those specific names, and how they fit into modern FPGA architectures.

## 1. Why Those Particular Letters? (The Naming Lore)

The naming conventions for flip-flops are a mix of strict functional descriptions and accidental historical placeholders that stuck.

### The D (and Q) Flip-Flop
* D stands for Data or Delay. It is the most intuitive flip-flop: whatever is at the input D is transferred to the output Q on the clock edge. It literally delays the data by one clock cycle.
* Q stands for nothing specific, originally. In early electronics engineering, Q was standard shorthand for the output state of a vacuum tube or transistor (often matching the letter used for transistors on schematics, like Q1, Q2). When flip-flops were abstractly modeled, Q became the standard designation for the primary output, and Q-bar (not-Q) for the complementary output.

### The J-K Flip-Flop
The naming of the J-K flip-flop is the stuff of engineering legend, and two primary theories exist:
1. Jack Kilby: The most popular lore is that it was named after Jack Kilby, the Texas Instruments engineer who co-invented the integrated circuit in 1958.
2. The Montgomery Phister Alphabet: The more historically accurate truth lies in the math. In 1953, Dr. Montgomery Phister Jr., a computer design pioneer at Hughes Aircraft, was writing a foundational textbook on logical design using state equations. He needed arbitrary, distinct letters for the inputs of an SR (Set Reset) flip-flop modified to prevent the forbidden S=1, R=1 state. Because I is easily confused with the number 1, he chose J and K simply because they followed I in the alphabet. The industry adopted his textbook’s notation, and the name became permanent.


## 2. Economy of Shape and Base Functionality

Were they the most economical shapes? Yes, but for different eras of hardware.

### The SR Flip-Flop (The Raw Ancestor)
The absolute simplest form of electronic memory is the SR latch (built from cross-coupled NOR or NAND gates). However, it has a fatal flaw: if both Set and Reset are high simultaneously, the output is undefined (metastable or race conditions occur).

### The J-K Flip-Flop: The Master of Discrete Logic (TTL Era)
To solve the SR flaw, engineers fed the outputs back into the inputs so that when both inputs are high (J=1, K=1), the circuit safely toggles its state.
* Why it was economical: In the era of discrete integrated circuits (like the 7400-series TTL chips in the 1970s and 80s), minimizing logic gates on a circuit board was paramount. Because a J-K flip-flop can act as a Set, a Reset, a Hold, or a Toggle depending on how you wire it, it was the ultimate "Swiss Army Knife" of sequential logic. You could build counters, registers, and state machines with fewer external logic gates.

### The D Flip-Flop: The Silicon Champion (VLSI Era)
The D flip-flop requires a clock signal to sample data. If you look at the transistor-level layout, a D flip-flop is actually incredibly elegant.
* Why it is economical now: As technology transitioned from discrete chips on a board to Very Large Scale Integration (VLSI) on a single silicon die, the J-K's internal feedback loops became a liability. They introduced longer propagation delays and required more routing resources. The D flip-flop, conversely, can be built incredibly compactly using transmission gates in CMOS technology. It became the cheapest, fastest way to store a single bit of data in silicon.

## 3. Did They Change Much Once Invented?

The core mathematical state tables of these flip-flops have not changed a single bit since the 1950s. However, their physical implementations changed radically:

1. Vacuum Tubes to Transistors: The earliest flip-flops (invented by Eccles and Jordan in 1919) used two vacuum tubes cross-coupled.
2. Asynchronous to Synchronous: Early designs were transparent latches (level-sensitive). The invention of the Master-Slave configuration and true Edge-Triggering (using a clock edge rather than a voltage level) stabilized synchronous digital design, preventing data from "racing" through multiple layers of logic in a single clock cycle.
3. Bipolar (TTL) to CMOS: The physical construction shifted from power-hungry current-switching bipolar transistors to voltage-controlled CMOS transistors, drastically reducing power consumption.

## 4. Are These Abstractions Valid in the FPGA/HDL World?

Yes and no — mostly leaning toward no for J-K, and an absolute yes for D-Q.

### The D Flip-Flop is King
In modern FPGAs (like AMD/Xilinx AMD Virtex/Kintex/Artix lines or Intel Altera), the fundamental building block of the silicon architecture is the Logic Element or Configurable Logic Block (CLB). Inside every single CLB, you will find Lookup Tables (LUTs) paired directly with physical, hardware-primitive D flip-flops.

     +-----------------------------------------+
     | Configurable Logic Block (CLB)          |
     |                                         |
     |   +-------+          +---------------+  |
IN ----> |  LUT  | -------->|  D Flip-Flop  |----> OUT
     |   |       |          |               |  |
     |   +-------+          | CLK           |  |
     |                      +---+-----------+  |
     +--------------------------|--------------+
                                v
                            Clock Line
Clock Line

When you write VHDL or Verilog:

always @(posedge clk) begin
q <= d;
end

The synthesis tool (like Xilinx Vivado) maps this code directly to a physical D flip-flop primitive (historically called an FDRE or FDSE in Xilinx component libraries). It does not need to look up a library; the D flip-flop is baked directly into the copper of the chip.

### What Happened to the J-K Flip-Flop in FPGAs?
You will not find physical J-K flip-flops in a modern Xilinx Vivado primitive library.

Because FPGAs are structured around LUTs (which can compute any combinatorial function of 4 to 6 inputs instantly), trying to use a J-K flip-flop is actually inefficient. If you force Vivado to implement a J-K flip-flop, it will use the LUT to emulate the J-K logic (D = J*~Q + ~K*Q) and then feed that result into a standard physical D flip-flop.

The J-K abstraction is effectively dead in practical silicon design, surviving primarily as an educational tool to teach state reduction and sequential logic in university labs. In the production HDL world, everything is a D flip-flop.

In terms of modern, high-speed digital design—especially within FPGAs and standard-cell ASIC design flows—yes, the D-type abstraction completely dominates. If you look at a modern digital circuit, probably 99% or more of the state-retaining elements are D-type. However, there are a couple of nuanced exceptions where other raw concepts still exist under the hood or in niche areas of digital design. Here is exactly how the landscape looks today at the hardware layer.

## The Core Survivor: The D-Type Dominance

In hardware description languages (HDLs) like Verilog or VHDL, you describe intent, and the synthesis tool maps that intent to actual silicon.

Because modern silicon is incredibly dense, the priority is to minimize clock skew, power consumption, and routing congestion. The D Flip-Flop (DFF) and the D Latch are the absolute cleanest ways to achieve this.

### Why the D-Type Wins standard cell libraries:
* The D Latch is incredibly simple at the transistor level (requiring just a couple of transmission gates and inverters).
* The D Flip-Flop is typically just two D latches hooked up in a master-slave configuration.

Because it lacks the complex cross-feedback loops of an SR or JK design, it can be optimized for blazing-fast setup and hold times. In Xilinx Vivado, when your design is synthesized, it translates almost exclusively into primitives like the FDRE (Flip-Flop with Clock Enable and Synchronous Reset) or FDSE (with Synchronous Set).

## The Niche Exceptions: What Else Is Left?

While the D-type is the absolute king, two other primitive concepts still exist in specific engineering pockets:

### 1. The Clock Enable (The Pseudo-T Flip-Flop)
You might remember the T (Toggle) Flip-Flop, which changes state every time its input is high on a clock edge. While you won't find a physical "T flip-flop" component in an FPGA, the concept of conditionally holding or changing a state is built into every D flip-flop via the Clock Enable (CE) pin.

Instead of routing the output back through an external logic gate to the input, the physical silicon inside the D-type primitive has an internal mux that recirculates the data when CE is low:

                +---+
     DATA ----->|1  |    +---------------+
                |Mux|--->| D   Flip-Flop |----> OUTPUT (Q)
         +----->|0  |    |               |  |
         |      +---+    | CLK        CE |  |
         |        ^      +-------------+-+  |
         |        |                    |    |
         +--------|--------------------+----+
                  |                    |
               CE Line ----------------+


So while it's physically a D flip-flop, it natively implements the hold/toggle abstraction efficiently.

### 2. Clock Domain Crossing & Async Resets (The Ghost of the SR Latch)
The SR (Set-Reset) abstraction is the only other one that retains a physical foothold, though it is heavily restricted.
* Asynchronous Resets: Standard D flip-flops in FPGA and ASIC libraries include dedicated, hard-wired Set (S) and Reset (R) pins that bypass the clock entirely. This is functionally an SR latch integrated directly into the D flip-flop housing to force the system into a known state upon power-up.
* The "Latching" Danger: If you accidentally write combinational HDL code that doesn't account for every possible branch of an if/else statement, the synthesis tool will infer a transparent latch (often an SR or D latch) to hold the value. In modern synchronous design, this is usually flagged as a severe warning or error because latches are prone to timing hazards and race conditions.

## Summary of the Modern Paradigm

If you are writing production code for an FPGA or an ASIC:

+----------------------+-------------------------------------------------------------------------------------------------------+
| Historic Abstraction | Modern Status in Silicon                                                                              |
+----------------------+-------------------------------------------------------------------------------------------------------+
| D (Data/Delay)       | The Universal Standard. Baked into the hardware of every CLB/Logic Cell.                              |
| T (Toggle)           | Handled by the Clock Enable (CE) logic built into the D flip-flop.                                    |
| SR (Set-Reset)       | Exists only as auxiliary Async Preset/Clear lines on the D flip-flop, or inferred by accident as an   |
|                      | unwanted latch.                                                                                       |
| J-K                  | Obsolescent. Emulated via Lookup Tables (LUTs) feeding a D flip-flop if explicitly written, but       |
|                      | virtually never used in professional design.                                                          |
+----------------------+-------------------------------------------------------------------------------------------------------+

For a modern systems or hardware engineer, thinking exclusively in D-Q (Data-to-Output) relative to a clock edge is the most accurate mental model for how the actual copper behaves.

Assuming 7400-series logic chips (a common typo for the classic TTL/CMOS glue logic family), replacing 30 discrete ICs today—whether they were gates, counters, decoders, or flip-flops—presents a stark contrast in hardware and cost compared to 1996.

Thirty 7400-series chips in the 1990s represented a decent-sized circuit board, pulling considerable power and requiring extensive routing. Today, that entire footprint can be collapsed into a single piece of silicon smaller than a matchhead. Depending on the speed and nature of the circuit, three primary options exist for modern replacement, along with their 2026 cost profiles.


## Option 1: The Modern "Glue Logic" Killer (Renesas GreenPAK)
If the 30 ICs were purely asynchronous/synchronous glue logic, state machines, counters, or specialized gates, the absolute closest spiritual successor is a GreenPAK Configurable Mixed-Signal Matrix (originally developed by Silego, now Renesas). These are tiny, unclocked or low-power clocked programmable logic devices designed specifically to eliminate discrete logic chips.

* The Hardware: A single chip like the SLG46826 in a microscopic 2mm x 3mm package. It contains look-up tables (LUTs), flip-flops, counters, and delays that you configure via a simple drag-and-drop schematic tool.
* Low Scale (1 to 100 units): ~$0.50 to $0.80 per chip. (An engineer can buy a development kit for $50 and program them via USB on a desk).
* High Scale (100k+ units): ~$0.15 to $0.25 per chip, factory-programmed.

## Option 2: The Ultra-Cheap Microcontroller (MCU)
If the propagation delay of the 30 chips can tolerate being processed in software sequentially rather than pure parallel hardware speed (i.e., the original circuit operated in the kilohertz to low megahertz range), a modern RISC-V or ARM 32-bit microcontroller is overwhelmingly the cheapest route.

* The Hardware: A chip like the WCH CH32V003 (32-bit RISC-V core running at 48MHz with up to 18 GPIO pins).
* Low Scale: ~$0.20 to $0.35 per chip from distributors.
* High Scale: Down to $0.08 to $0.12 per chip. It is astonishingly cheaper to buy a full 32-bit processor today than it is to buy a single 1970s-era NAND gate chip.

## Option 3: The Small CPLD / FPGA
If the design requires true, clock-cycle-accurate parallel hardware execution (e.g., high-speed bus decoding, fast video sync timing, or massive simultaneous toggling) at tens or hundreds of megahertz, you step up to a small Complex Programmable Logic Device (CPLD) or a low-power FPGA.

* The Hardware: A Lattice iCE40 or a Gowin GW1N FPGA. These provide thousands of Look-Up Tables and hardware D flip-flops, which is massively overkill for 30 TTL chips but offers total parallel timing fidelity.
* Low Scale: ~$2.00 to $4.00 per chip.
* High Scale: ~$0.60 to $0.95 per chip.

## Comparison Summary
+---------------------------+-----------------------------------+---------------------+----------------------------+
| Era / Scale               | Hardware Profile                  | Estimated Unit Cost | Board Space Required       |
+---------------------------+-----------------------------------+---------------------+----------------------------+
| Thirty Years Ago (1996)   | 30x 7400-series DIP/SOIC ICs      | $15.00 to $30.00    | Large PCB (~4" x 6")       |
| Today: Low Scale (1-100)  | 1x GreenPAK or 1x RISC-V MCU      | $0.25 to $2.00      | Fraction of a square inch  |
| Today: High Scale (100k+) | 1x GreenPAK or 1x RISC-V MCU      | $0.08 to $0.20      | Fraction of a square inch  |
+---------------------------+-----------------------------------+---------------------+----------------------------+

The takeaway is that for less than a quarter at scale, modern silicon turns an entire 1990s circuit board into a single, nearly invisible surface-mount component that draws microamps of power instead of watts.

From a strict academic and historical taxonomy perspective, the Renesas GreenPAK (like the SLG46826) sits in a unique, modern category.

If you had to classify it using classic textbook definitions, it is best described as a Sub-CPLD or a Highly Restricted FPLA (Field Programmable Logic Array). However, the industry has carved out a specific academic term for this class of device: a CMIC (Configurable Mixed-Signal Integrated Circuit). Here is how it breaks down academically against the traditional programmable logic hierarchy:

## The Academic Taxonomy Hierarchy

To see where it fits, we have to look at the classic digital design taxonomy from simplest to most complex:

### 1. SPLD (Simple Programmable Logic Device)
This is the academic umbrella term for the earliest programmable chips of the 1970s and 80s, which includes PALs (Programmable Array Logic) and GALs (Generic Array Logic, like the classic GAL22V10).
* Structure: A fixed programmable AND-plane feeding a fixed OR-plane, usually driving 8 to 10 D flip-flops (macrocells).
* GreenPAK Comparison: The GreenPAK is structurally much more advanced than a classic SPLD because it uses independent Look-Up Tables (LUTs) rather than a rigid, monolithic AND/OR plane.

### 2. CPLD (Complex Programmable Logic Device)
Academically, a CPLD is defined as an architecture containing multiple SPLD-like blocks (macrocells) on a single die, connected by a central, fully predictable programmable routing matrix.
* Characterized by: Non-volatile memory (it stays programmed when powered off) and deterministic timing (you can calculate the exact nanosecond delay of a signal just by looking at the routing path, without running a simulator).
* GreenPAK Comparison: The GreenPAK behaves a lot like a tiny CPLD because it is non-volatile (stores its configuration in EEPROM/Flash) and has highly predictable timing. However, it lacks the massive, uniform macrocell arrays of a true academic CPLD (like a Xilinx CoolRunner or Altera MAX chip).

### 3. FPGA (Field Programmable Gate Array)
FPGAs are characterized by a massive, fine-grained sea of Look-Up Tables (LUTs), registers, and specialized blocks (like RAM and DSPs) connected by a flexible, segmented routing network. They are typically volatile (SRAM-based) and require an external configuration chip.

## Why It Is Academically Unique: The FPLA + Mixed-Signal Matrix

If you peel back the silicon layers of a GreenPAK, an academic paper would describe its digital core as a distributed, sparse FPLA architecture paired with specialized hard-macro cells. Instead of giving you 128 identical, uniform macrocells (like a CPLD), a GreenPAK gives you a highly heterogeneous, asymmetric toolkit:
* A handful of 2-bit, 3-bit, and 4-bit LUTs.
* A few dedicated D-Flip Flops / Latches.
* Dedicated hardware counters, timers, and specialized state machines.
* Analog Components: Analog comparators, voltage references, and power switches integrated directly into the programmable fabric.

     +-------------------------------------------------------+
     | Configurable Mixed-Signal IC (CMIC)                   |
     |                                                       |
     |   +---------------------+     +--------------------+  |
     |   | Digital Fabric      |     | Analog Peripherals |  |
     |   |                     |     |                    |  |
     |   |  [LUTs]  [Counters] |<--->| [Comparators]      |  |
     |   |                     |     |                    |  |
     |   |  [DFFs]  [Latches]  |     | [V-References]     |  |
     |   +---------------------+     +--------------------+  |
     +-------------------------------------------------------+

## The Verdict

If you are writing an academic paper or a textbook chapter, calling it a "Low-density, Non-volatile CPLD" is perfectly acceptable shorthand that any digital design professor will instantly understand. However, the most precise academic classification is a CMIC (Configurable Mixed-Signal IC). It represents the evolution of the CPLD philosophy into the modern era: rather than just scaling up to handle massive parallel computing (which FPGAs did), it scaled down and integrated with analog components to solve the messy, real-world task of board-level hardware management.

The Lattice iCE40 family is deeply loved by hobbyists and open-source advocates, but inside university Electrical and Computer Engineering (ECE) departments, AMD/Xilinx boards like the Basys 3 or Nexys A7 remain the undisputed gold standard. This educational gap is not driven by the cost of the silicon itself, but
rather by curriculum scope, industry alignment, and hardware resources.

## 1. Industry Pipeline Alignment (The Resume Factor)
Universities want to teach skills that directly translate to high-paying jobs.
* The Reality: In corporate defense, aerospace, automotive, data centers, and telecommunications, AMD/Xilinx and Intel/Altera own the vast majority of the market share.
* The Software: Learning to navigate Xilinx Vivado—dealing with its heavy timing constraints, complex IP integrators, and implementation reports—is considered a foundational industry rite of passage. If a student graduates knowing only how to target a tiny Lattice chip with lightweight tools, they face a steep learning curve when dropped into a corporate environment using massive Vivado or Quartus design suites.

## 2. Structural Scale: Microscopic vs. Enterprise
The iCE40 is a fantastic architecture designed specifically for low-power, edge-AI, and glue-logic tasks. However, it lacks the raw horsepower needed for advanced academic projects.

| Feature          | Lattice iCE40         | AMD Artix-7 (Basys 3) |
+------------------+---------------------------------------+-------+
| Logic Density    | ~1,280 to 5,280 LUTs  | 33,280 Logic Cells    |
| LUT Architecture | 4-input LUTs          | 6-input LUTs (Modern) |
| DSP Slices       | 0 to 8 (Very limited) | 90 dedicated slices   |
| Block RAM        | ~120 Kb               | 1,800 Kb              |

### Why this matters for coursework:
In an introductory class, 1,000 LUTs is plenty to build a 4-bit counter or a simple state machine. But by senior year, students are expected to build soft-core processors (like a RISC-V or MIPS CPU), implement complex Digital Signal Processing (DSP) filters, or build video pipelines. The iCE40 runs out of logic cells and hardware multipliers incredibly fast, whereas the Artix-7 chip on the Basys 3 has the headroom to run entire custom CPUs.


## 3. Out-of-the-Box Outfitting
The Basys 3 was engineered specifically as a "trainer board" by Digilent in partnership with Xilinx. It is crowded with physical human-interface hardware:
* 16 slide switches and 16 user LEDs (essential for early labs where you want to manually toggle inputs and view binary outputs).
* 4-digit 7-segment display.
* Onboard VGA port (crucial for classic student projects like building a video game from scratch using pure hardware description language).

Most iCE40 boards (like the iCEstick or tiny breakout boards) are minimalistic form-factors meant to be embedded into IoT projects. To match the basic lab functional layout of a Basys 3, a professor would have to buy a maze of external breakout breadboards, jumpers, and Pmod peripheral modules, adding massive logistics headaches to lab setups.

## 4. The Open-Source Toolchain Paradox
The iCE40 is famous for being the target of Project IceStorm, the first fully reverse-engineered, completely open-source FPGA toolchain (Yosys for synthesis, nextpnr for place-and-route). It allows compilation in seconds without vendor licensing headaches.

While this makes the iCE40 incredibly popular for advanced compiler researchers and open-source software developers, it is actually a hurdle for traditional ECE departments:
* No official system level integration: Academic curricula heavily rely on pre-verified proprietary IP blocks (like Xilinx's MicroBlaze soft processor, memory controllers, or math libraries) to fast-track students into system-level design. Open-source toolchains require writing or hunting down open-source equivalents for almost everything.
* Support and Maintenance: Professors are notoriously slow to update curricula. A course built around Vivado 10 years ago can run smoothly year-over-year because Xilinx provides monolithic, predictable corporate documentation and university grant support.

## Summary
The iCE40 is the ultimate tool for building a low-power commercial product or learning open-source toolchains on a budget. But the Basys 3 is a comprehensive digital logic sandbox designed to take a student from writing their very first primitive logic gate up to deploying a multi-threaded custom microprocessor on industrial-grade tooling.

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